Semiconductor Repair Analysis Device for Reducing Area Overhead
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing area overhead and increasing analysis speed for repair solutions, as conventional methods either increase area overhead or fail to secure optimal repair solutions and analysis results due to insufficient fault address storage and complex fault distributions.
Innovation Solution
A repair analysis device and method that selects and analyzes row and column addresses of spare pivot fault cells using a control code, generating signals to determine inclusion of non-spare pivot fault cells, thereby optimizing repair rates and reducing area overhead through efficient fault information storage and analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate auxiliary operation circuits are installed for all redundancy cases (CRESTA method), then the repair rate and analysis operation speed are optimized, but the area overhead exponentially increases with the number of redundancy cells
Solution Approach 1:
The patent segments the fault analysis process by dividing fault cells into two categories: spare pivot fault cells and non-spare pivot fault cells. This segmentation allows the system to focus auxiliary operation circuits only on spare pivot cases, reducing the number of required circuits from exponential to linear scale while maintaining complete repair coverage through systematic analysis of both fault types
Solution Approach 2:
The patent introduces a control code as an intermediary that coordinates between the selection unit and analysis unit. The control code enables a single auxiliary operation circuit to dynamically handle different repair scenarios by selecting appropriate fault cell combinations, replacing the need for separate dedicated circuits for each redundancy case
2Speed
If fault address collecting process is performed during test process (ESP method), then the analysis speed of self-repair circuit is increased, but the register capacity for storing fault addresses is insufficient to accurately reproduce fault phenomenon
Solution Approach 1:
The patent extracts only the essential fault information needed for repair analysis by identifying and storing specifically the spare pivot fault cell addresses and their associated non-spare pivot fault cells. This selective extraction reduces the storage burden while maintaining sufficient information to reproduce and analyze all fault phenomena, eliminating the need to store complete fault address maps
Solution Approach 2:
The patent changes the storage parameter from complete fault address maps to a condensed representation using spare pivot fault cell identifiers and control codes. This parameter transformation maintains the ability to reproduce fault phenomena while significantly reducing register capacity requirements and improving analysis speed through more efficient data structures
3Area of stationary object
If branch-and-bound algorithm with must-repair line exclusion is used (intelligent solve first method), then the area overhead is reduced, but the analysis operation time excessively increases when the number of faults increases or distribution becomes complicated
Solution Approach 1:
The patent performs preliminary classification of fault cells into spare pivot and non-spare pivot categories before the actual repair analysis. This preliminary action organizes the fault data in advance, enabling the analysis unit to quickly process fault combinations without requiring complex branch-and-bound algorithms, thus reducing analysis operation time while maintaining low area overhead
Solution Approach 2:
The patent implements a dynamic analysis approach where the control code adaptively selects which spare pivot fault cells to analyze based on the current fault distribution. This dynamic selection allows the system to efficiently handle varying fault patterns and distributions without requiring excessive analysis time or complex algorithmic structures
Data Source
AI summary
A device for repair analysis includes a selection unit and an analysis unit. The selection unit is configured to select a part of the row addresses of a plurality of spare pivot fault cells and a part of the column addresses of the spare pivot fault cells in response to a control code. The analysis unit is configured to generate an analysis signal indicating whether row addresses of a plurality of non-spare pivot fault cells are included in selected row addresses and column addresses of the non-spare pivot fault cells are included in selected column addresses.