Semiconductor Repair Control Device for Memory Yield
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Solution Overview
Problem
The inefficiency in semiconductor devices due to defects in memory cells leads to high product yield loss, as entire devices are discarded due to a small number of defective cells, and existing redundancy systems require additional circuits for storing failed addresses, further reducing yield.
Innovation Solution
A repair control device with a failed address storage circuit, address comparison circuit, and address generation circuit that sorts and stores failed addresses, allowing for efficient matching and generation of access target addresses, reducing the need for additional circuits and improving operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of failed cells increases, then the number of failed addresses increases, but the number of circuits required for storing failed addresses increases, reducing yield
Solution Approach 1:
The patent combines multiple failed address information into a single compressed representation. Instead of storing each failed address separately, the system merges redundant information and stores only essential unique identifiers, reducing the total storage requirements while maintaining complete defect coverage capability
Solution Approach 2:
The storage circuit is designed to handle multiple types of address information (bank addresses, row addresses, column addresses) using a unified storage structure. This multi-functional approach allows the same storage resource to serve multiple purposes, reducing overall circuit complexity while maintaining comprehensive failed address storage capability
2Reliability
If traditional redundancy systems are used, then defective cells can be repaired, but additional circuits for storing failed addresses are required, further reducing yield
Solution Approach 1:
The patent extracts only the essential information needed for repair operations from the complete failed address data. By taking out only the critical address components required for redundancy activation, the system eliminates unnecessary storage overhead while preserving full repair functionality
Solution Approach 2:
The system changes the representation parameters of failed address storage from storing complete address tuples to storing compressed index information. This parameter transformation reduces the storage footprint significantly while maintaining the ability to retrieve and use full address information when needed for repair operations
Data Source
AI summary
A repair control device for memory cells divided into a plurality of banks may include a failed address storage circuit configured to sort and store a plurality of failed addresses each containing a failed bank address and a failed row address, according to the failed row address, and store the failed row address by matching the failed row address with total failed bank information representing one or more failed banks indicated by the failed row address. The repair control device also includes an address comparison circuit configured to compare an input address to a pair comprised of the failed row address and the total failed bank information, stored in the failed address storage circuit, and generate a hit signal based on the comparison result. The repair control device further includes an address generation circuit configured to generate an access target address based on the hit signal.