Semiconductor Repeater Placement in Stacked Wiring Layers
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Solution Overview
Problem
The existing methods for reducing timing delays in semiconductor devices, such as inserting repeater cells in long-distance wires, often increase manufacturing costs and reduce memory cell density, making miniaturization difficult due to the need for layout changes in multiple wiring layers and the substrate.
Innovation Solution
Forming repeaters using transistors in the upper portions of stacked wiring layers to reduce timing delays, allowing for correction without extensive redesign of the substrate layout, thus minimizing manufacturing costs and maintaining high memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If repeater cells are inserted in long-distance wires to reduce timing delays, then timing delay is reduced, but manufacturing cost increases and memory cell density decreases
Solution Approach 1:
The patent forms repeater transistors in upper wiring layers (e.g., third wiring layer) instead of in the substrate plane, utilizing the vertical dimension of stacked wiring layers. This allows repeaters to be integrated without occupying additional substrate area, thus reducing timing delay while maintaining memory cell density
2Loss of time
If repeater cells are inserted in long-distance wires to reduce timing delays, then timing delay is reduced, but manufacturing cost increases
Solution Approach 1:
The patent combines the formation of repeater transistors with existing wiring layer formation processes. The repeater transistors are formed using the same manufacturing steps as the surrounding circuit wiring layers, merging two functions into one process sequence and eliminating the need for separate repeater fabrication steps, thus reducing manufacturing cost
3Loss of time
If MOSFETs are newly provided in the vicinity of the main surface to correct timing, then timing delay is reduced, but layout changes are required increasing manufacturing cost
Solution Approach 1:
The patent moves repeater transistor formation from the substrate plane to upper wiring layers, changing the spatial dimension where repeaters are implemented. This eliminates the need to redesign substrate layouts and wiring layer connections, as repeaters are formed in-place within the existing upper wiring layer structure
Data Source
AI summary
In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.