Semiconductor Device Replacement Gate Contact Formation
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Solution Overview
Problem
The existing semiconductor manufacturing processes face challenges in forming small contact holes, leading to short circuits and process defects due to differing etching depths and small width-to-height ratios, which complicates the selection of processes and increases parasitic resistance.
Innovation Solution
A method is developed to form first and second contacts in two steps, where the first contacts and replacement gate are formed using the same conductive material, simplifying the process and ensuring uniform etching depth, and a liner can serve as a work function tuning layer to further simplify the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If contacts are formed in a single step, then process complexity is reduced, but etching depth uniformity cannot be achieved leading to short circuits and defects
Solution Approach 1:
The contact formation process is divided into two distinct steps: first forming bottom contacts at source/drain regions, then forming top contacts at gate and source/drain regions. This segmentation allows each etching step to be optimized independently, achieving uniform etching depth for each contact type while maintaining manageable process complexity.
Solution Approach 2:
The first interlayer dielectric layer is deposited and planarized to expose the gate before forming contact holes. This preliminary planarization action creates a uniform starting surface that enables precise control of etching depth in subsequent steps, ensuring uniform contact formation.
2Adaptability or versatility
If different materials are used for gate metal and contact hole metal, then functional requirements are met, but process steps increase
Solution Approach 1:
The first conductive material layer serves multiple functions: it forms the gate electrode in the gate region and simultaneously forms the bottom contacts in the source/drain regions. This multi-functionality reduces the number of deposition steps while meeting the functional requirements of both gate and contact structures.
Solution Approach 2:
The formation of gate electrode and bottom contacts is merged into a single deposition step using the first conductive material. This combining of operations simplifies the overall process flow while maintaining the ability to differentiate functions through subsequent selective removal of the sacrificial gate.
Data Source
AI summary
There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region. Thereby, the replacement gate and the first contacts can be made in one same step of depositing the same material, and thus the process flows are simplified.