Semiconductor Device Replica Cell Programming Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with one-time programmable (OTP) memory cells, the inspection time for ensuring proper programming is lengthy due to the need for loop processing to verify successful data programming, which increases chip area and manufacturing costs.
Innovation Solution
The implementation of a semiconductor device configuration that includes a normal cell, a replica cell, a bias generation circuit, and a current generation circuit, allowing for the inspection of programming success without loop processing by generating a reference current based on the bias from the replica cell's equivalent characteristics, thereby reducing inspection time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If loop processing is used to verify programming success, then programming accuracy is improved, but inspection time increases
Solution Approach 1:
The patent uses a replica cell that copies the structure and characteristics of the normal memory cell to perform threshold voltage verification. The replica cell is programmed in parallel with the normal cell during manufacturing, and its threshold voltage is measured to determine programming success without requiring loop verification of the actual data cell, thus reducing inspection time while maintaining accuracy
Solution Approach 2:
The replica cell is programmed in advance alongside the normal cell during the manufacturing process. This preliminary programming action allows the threshold voltage characteristics to be established before final inspection, enabling a single-shot verification measurement rather than requiring iterative loop processing
2Reliability
If verification circuits are added to ensure programming success, then reliability is improved, but chip area increases
Solution Approach 1:
The replica cell serves multiple functions: it acts as both a threshold voltage reference and a verification mechanism. By using the same cell structure for both data storage (normal cell) and verification (replica cell), the patent eliminates the need for separate dedicated verification circuits, thereby maintaining reliability while minimizing chip area
Solution Approach 2:
Instead of adding complex verification circuits, the patent creates a simplified copy (replica cell) of the memory cell structure that can be used for verification purposes. This copy approach provides reliable verification functionality with minimal additional area overhead compared to full verification circuit implementations
3Productivity
If replica cell is used for threshold voltage measurement, then inspection speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into normal cells for data storage and replica cells for verification. This segmentation allows independent optimization of each cell type and enables parallel processing during manufacturing, improving inspection speed without significantly increasing overall device complexity
Solution Approach 2:
The replica cell is a simplified copy of the normal cell structure, designed specifically for threshold voltage measurement. By using a copy approach rather than creating entirely new verification circuitry, the patent achieves fast inspection speed while keeping the increase in device complexity minimal and manageable
Data Source
AI summary
A semiconductor device which includes a normal cell, a replica cell, a word line, a first bit line, a bias generation circuit, a second bit line, and a current generation circuit. The normal cell is a one-time programmable (OTP) type memory cell. The replica cell has characteristics equivalent to those of the normal cell. The word line is electrically connected in common to a control terminal of the normal cell and a control terminal of the replica cell. The first bit line is electrically connected to an input-output terminal of the replica cell. The bias generation circuit is electrically connected to the first bit line. The second bit line is electrically connected to an input-output terminal of the normal cell. The current generation circuit is electrically connected to the second bit line. The bias generation circuit and the current generation circuit are controlled through a common control line.