Semiconductor Control Circuit for Fast Reset via Dynamic Clock Frequency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND type flash memory devices, the reset command process is time-consuming due to the need for electrical discharge of high and mid voltages, which can damage the memory if not executed promptly, and requires many clock cycles, reducing the margin between actual and specified reset times.
Innovation Solution
A control circuit that generates a system clock with a higher frequency upon receiving a reset command, allowing for a faster transition into a reset sequence mode, thereby shortening the electrical discharge time and reducing the number of clock cycles required for the reset process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset command process is executed using a normal frequency system clock, then the electrical discharge process can be completed safely, but the reset time becomes too long and reduces the margin between actual and specified reset times
Solution Approach 1:
The system clock frequency is dynamically adjusted based on the operational mode. During reset command processing, the clock frequency is increased from normal frequency to high frequency, enabling faster execution of electrical discharge operations while maintaining safety through controlled frequency switching
Solution Approach 2:
The clock frequency parameter is changed from normal to high when a reset command is detected. This parameter change accelerates the reset process by increasing the processing speed of electrical discharge operations, reducing the time margin issue while completing the safety-critical discharge function
2Loss of time
If the system clock frequency is increased to speed up the reset process, then the reset time is reduced, but the risk of memory damage increases due to incomplete electrical discharge
Solution Approach 1:
The control circuit continuously monitors the reset command state and automatically adjusts the clock frequency accordingly. When a reset command is detected, the system switches to high frequency mode; when the reset process completes, it returns to normal frequency, providing feedback-controlled frequency adjustment that balances speed and safety
Solution Approach 2:
The control circuit autonomously manages the clock frequency adjustment without external intervention. It detects reset commands, switches to high frequency mode for accelerated processing, and automatically returns to normal mode after completion, making the system self-regulating for both performance and safety
3Reliability
If many clock cycles are used for the reset process, then the electrical discharge can be completed thoroughly, but the productivity of the semiconductor device decreases
Solution Approach 1:
The clock frequency is dynamically switched between normal and high frequencies based on operational requirements. During reset operations requiring thorough electrical discharge, high frequency mode reduces the number of clock cycles needed, thereby maintaining discharge completeness while improving device throughput
Solution Approach 2:
The system employs periodic frequency switching where high frequency operation is activated only during reset command processing and normal frequency is used during other operations. This periodic adjustment ensures thorough discharge when needed while maximizing productivity during standard operations
Data Source
AI summary
In a semiconductor device, the reset command input process may be executed by a simple method and circuit in a short period of time when a reset command is inputted compared to conventional art. A control circuit for the semiconductor device is adapted to control a clock generator for generating a system clock having a changeable frequency, wherein, in a normal operating mode of the semiconductor device, the control circuit changes the frequency of the system clock generated by the clock generator from a first frequency to a second frequency that is higher than the first frequency according to a reset command, and performs an interrupt process on the semiconductor device, so as to enter a reset sequence mode from the normal operating mode.