Semiconductor Device Reset Data Integrity Verification
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Solution Overview
Problem
Existing semiconductor devices are vulnerable to Fault Injection Attacks (FIA) during reset transfer, which can alter the security protection state and lead to unauthorized control or data leakage.
Innovation Solution
A semiconductor device with a processor, memory controller, reset data transfer controller, and system controller, which performs multiple data transfers during reset, using a first register for initial settings and a second register for verification, and outputs a determination result signal to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double check using software is performed after processor startup, then security protection state can be verified, but it cannot be applied during reset transfer when processor is not yet running
Solution Approach 1:
The patent performs the double-check verification action during the reset transfer process itself, before the processor starts running. The memory controller executes multiple data transfer operations and comparisons in advance, during the reset sequence, so that when the processor eventually starts, the security verification has already been completed. This resolves the contradiction by performing the verification action in the preliminary reset phase rather than waiting for processor startup.
2Reliability
If multiple data transfers are performed during reset transfer, then data integrity can be verified, but the reset transfer process becomes more complex
Solution Approach 1:
The memory controller is designed to perform multiple functions during the reset transfer process: it executes data transfer operations, performs comparisons between transferred data, and manages the verification logic. By consolidating these multiple functions within the existing memory controller rather than adding separate verification hardware, the patent achieves data integrity verification without proportionally increasing device complexity.
Solution Approach 2:
The patent transfers the same data multiple times during reset transfer and uses comparisons to verify integrity. This involves creating multiple copies of the data in different registers and then comparing them. The duplication of data transfer operations enables verification while the comparison mechanism provides the security check, achieving reliability through a systematic copying and verification approach.
Data Source
AI summary
A semiconductor device is protected from glitch attacks (FIA). A reset data transfer controller RDTC executes N times of data transfer, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer, and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparison circuit CMP1 determines the match/mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs, and outputs a determination result signal RS representing the determination result. A system controller SYSC activates a processor PRC when the determination result signal RS indicates a match, and causes the reset data transfer controller RDTC to execute the N times of data transfer again when it indicates a mismatch.