Semiconductor Resin Alignment via Substrate Marks

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Solution Overview

Problem

The challenge in semiconductor device manufacturing is to ensure precise alignment and increased adhesion between the sealing resin and substrate, particularly as device sizes decrease, to prevent issues like wire short-circuiting and separation, while achieving higher output and reliability.

Innovation Solution

A method involving the use of marks in the X-axial direction on a substrate for precise placement of semiconductor elements, continuous application of sealing material along these marks, and dicing the substrate and sealing member in the Y-axial direction to form cut planes, ensuring accurate positioning and enhanced adhesion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the size of semiconductor device is reduced, then higher output and brightness are achieved, but resin misalignment and adhesion problems occur

Engineering Contradiction:
ImprovebrightnessVSAvoidresin alignment precision
Core Design Contradiction:
Illumination intensityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming marks on the substrate before mounting semiconductor elements and before applying sealing resin. These marks serve as pre-established alignment references that guide the subsequent positioning of sealing resin, ensuring precise placement even as device sizes are reduced. The marks are formed in advance to prevent misalignment issues that arise in miniaturized devices.

Inventive Principle:
Principle #10Preliminary action

2Volume of moving object

If the contact surface area between sealing resin and substrate decreases, then smaller device size is achieved, but adhesion between sealing resin and substrate deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoidadhesion strength
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent applies local quality by creating a roughened surface layer on the substrate within the sealing resin contact region. This local surface modification increases the contact area and adhesion strength between the sealing resin and substrate specifically where needed, without affecting the overall device size. The roughened surface provides enhanced mechanical interlocking and chemical bonding areas, solving the adhesion problem in miniaturized devices.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If marks are used for resin alignment, then precise resin placement is achieved, but additional manufacturing steps are required

Engineering Contradiction:
Improveresin placement precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the mark formation process with the existing semiconductor manufacturing process flow. The marks are formed using standard photolithography and etching techniques that are already part of the fabrication process, integrating the alignment reference creation into existing manufacturing steps rather than adding completely separate processes. This reduces the impact on manufacturing complexity while achieving precise resin placement.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7915090B2Method for manufacturing a semiconductor device
Publication Date: 2011.03.29 NICHIA CORP
  • US7915090B2 patent drawing
  • US7915090B2 patent drawing
  • US7915090B2 patent drawing

AI summary

A method for manufacturing a semiconductor device having a substrate on which conductor wiring is disposed, electrodes provided to the conductor wiring, a semiconductor element connected to the electrodes, and a sealing member that covers the semiconductor element, comprises; mounting a plurality of semiconductor elements on the substrate in the X-axial direction and the Y-axial direction, forming marks in the X-axial direction, supplying the sealing material onto the substrate to continuously-covering the plurality of semiconductor elements arranged in the X-axial direction along the marks, dicing the sealing member and the substrate in the Y-axial direction to form cut planes of the sealing member and the substrate in substantially one plane and being a pair of cut planes opposite one another.