Semiconductor Resist Structure for Stepped Electrode Area Control
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Solution Overview
Problem
The formation of unnecessary stepped regions in stacked electrode layers during semiconductor device manufacturing increases the memory chip area, as existing techniques like resist slimming and etching combination lead to inefficient area utilization.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a first and second resist, with a third film acting as an etching stopper, selectively etching exposed surfaces, and repeated etching and slimming steps to restrict the formation of stepped regions, thereby controlling the chip area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If resist slimming and etching techniques are combined to form stepped electrode layers, then the electrode layers can be formed in a stepped configuration, but unnecessary stepped regions are formed which increases the memory chip area
Solution Approach 1:
The patent divides the resist structure into multiple segments (first resist, second resist, third resist) with different functions. The first resist defines the contact hole pattern, the second resist forms the stepped structure, and the third resist refines the final pattern. This segmentation allows precise control of stepped regions while preventing unnecessary area expansion.
Solution Approach 2:
Different regions of the resist structure are given different qualities and functions. The first resist is optimized for contact hole definition, the second resist for stepped region formation, and the third resist for final pattern refinement. This local differentiation enables precise control of where stepped regions form, eliminating unnecessary area expansion while maintaining the required stepped configuration.
2Area of stationary object
If multiple etching and slimming steps are performed to control stepped region formation, then chip area expansion is suppressed, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the first resist and defining the contact hole pattern before subsequent etching steps. The second resist is then formed to create the stepped structure, followed by the third resist for final refinement. This preliminary structuring of the resist system before etching simplifies the overall process control compared to attempting to form stepped regions through multiple iterative etching and slimming cycles.
Solution Approach 2:
The patent introduces the second resist as an intermediary layer between the first resist (contact hole definition) and the final stepped electrode structure. This intermediary resist enables controlled formation of stepped regions during etching, allowing area suppression while maintaining process feasibility. The third resist then acts as a final intermediary for pattern refinement, reducing the need for complex iterative adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively suppresses the increase in chip area by precisely defining the stepped regions, ensuring efficient use of space and reducing unnecessary chip area expansion.
Implementation Method 1
forming a first resist and a second resist and a third film on a stacked body that includes a plurality of first films and a plurality of second films
Implementation Method 2
performing a first etch of the stacked body from an upper surface thereof using the first resist, the second resist, and the third film as a mask
Data Source
AI summary
A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a plurality of second films, the second resist facing one or more side surfaces of the first resist; forming a third film in a slit between the first resist and the second resist, the third film covering the side surfaces of the first resist and defining exposed surfaces of the first resist not covered by the third film; performing a first etch of the stacked body from an upper surface using the first resist, the second resist, and the third film as a mask; selectively etching the one or more exposed surfaces of the first resist and the second resist; and performing a second etch of the stacked body from the upper surface using the first resist and the third film as a mask.