Patterning Scheme for Semiconductor Resist Strip

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Solution Overview

Problem

Current strip technologies for semiconductor structures, particularly in 3D finFET technologies, face challenges such as substrate damage, dopant bleaching, and unbalanced strip times, leading to device degradation and issues like high-k dielectric and workfunction metal damage, especially in high-aspect ratio structures.

Innovation Solution

A patterning scheme is implemented where a second polymer layer is applied over open areas to balance strip times between exposed and protected device areas, using masking materials with the same or similar removal rates to minimize ashing time and prevent over-etching, thereby protecting workfunction metals and high-k dielectric materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If fluorine-containing chemistries are used for resist strip, then crust breakthrough and residue removal are effective, but substrate damage and dopant bleaching occur

Engineering Contradiction:

Improveresist strip effectivenessVSAvoidsubstrate damage

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent segments the resist strip process into multiple stages: first using fluorine-containing chemistry for crust breakthrough and residue removal, then switching to oxidizing chemistry or forming gas for complete strip. This segmentation allows each chemistry to perform its optimal function while minimizing harmful effects.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by first removing the resist crust with fluorine-containing chemistry before applying oxidizing chemistry or forming gas. This preliminary crust removal reduces the overall exposure time to damaging chemistries and prevents dopant bleaching during the main strip process.

Inventive Principle:

Principle #10Preliminary action

2Object-affected harmful factors

If oxidizing chemistries are used for resist strip, then substrate oxidation is reduced, but epitaxial erosion and TiN interaction with workfunction metals occur

Engineering Contradiction:

Improvesubstrate oxidationVSAvoidepitaxial erosion

Core Design Contradiction:

Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent segments the strip process to use oxidizing chemistry or forming gas only after fluorine-containing chemistry has removed the resist crust. This segmentation limits the exposure time to epitaxial-eroding chemistries while maintaining low substrate oxidation benefits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by removing the resist crust with fluorine-containing chemistry before applying oxidizing chemistry or forming gas. This preliminary step reduces the overall exposure time to damaging chemistries and prevents dopant bleaching during the main strip process.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If unbalanced strip time is used for open FET vs non-open FET, then complete OPL removal is achieved, but workfunction metal and high-k dielectric damage occurs

Engineering Contradiction:

ImproveOPL removal completenessVSAvoiddevice leakage

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by using different masking strategies for open FET and non-open FET areas. A first mask protects non-open areas during initial processing, and a second mask is applied to balance the strip time for OPL removal between different device regions, preventing over-etching in protected areas.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies preliminary action by protecting non-open FET areas with a first mask before OPL removal, then applying a second mask to balance strip times. This preliminary protection prevents workfunction metal and high-k dielectric damage during the OPL stripping process.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces device degradation by balancing strip times, minimizing substrate loss and damage to workfunction metals and high-k dielectric materials, enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

protecting the workfunction material over a second device area of the structure with a first masking material

Methodology Applied

Scientific EffectMasking:

Implementation Method 2

the first masking material and the second masking material having a same or substantially the same removal rate

Methodology Applied

Scientific EffectSelective removal:

Data Source

PatentUS9627272B2Patterning scheme to minimize dry/wets strip induced device degradation

Publication Date: 2017.04.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.