Semiconductor Resistance Control Layer Segmentation
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in designing appropriate electrostatic capacitance and electrical resistance due to high implantation energy requirements for ion implantation in resistance isolation regions, making it difficult to control resistance values uniformly.
Innovation Solution
A semiconductor apparatus with a resistance control layer comprising a low resistance region and a high resistance region, where the low resistance region electrically connects the semiconductor substrate to the second electrode, and the high resistance region has a higher resistivity, allowing for adjustable resistance values and improved circuit design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high implantation energy is used to uniformly increase resistance in the thickness direction, then resistance uniformity is improved, but control of resistance value becomes difficult
Solution Approach 1:
The resistance isolation region is divided into multiple regions with different impurity concentrations (first region with first concentration, second region with second concentration). This segmentation allows different portions to contribute differently to the overall resistance, enabling precise control of total resistance while maintaining uniformity through the layered structure.
Solution Approach 2:
Different regions within the resistance isolation region are assigned different impurity concentrations tailored to their specific functions. The first region has higher impurity concentration for lower resistance, while the second region has lower impurity concentration for higher resistance, optimizing local electrical properties to achieve both uniformity and controllability.
2Manufacturing precision
If the semiconductor substrate dimensions are changed to adjust resistance, then resistance value is improved, but electrostatic capacitance becomes difficult to design
Solution Approach 1:
The resistance isolation region is segmented into multiple regions with different impurity concentrations, allowing resistance to be controlled through concentration ratios rather than dimensional changes. This preserves the substrate dimensions needed for proper electrostatic capacitance design while achieving resistance control through the layered impurity structure.
Solution Approach 2:
Instead of changing physical dimensions to control resistance, the invention changes the electrical parameter (impurity concentration) in different regions. By adjusting the ratio of impurity concentrations between the first and second regions, the resistance value can be precisely controlled without altering the substrate dimensions that determine electrostatic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables easier adjustment of resistance values and enhances the degree of freedom in circuit design, reducing manufacturing costs and defects while maintaining stable resistance values across semiconductor apparatuses.
Implementation Method 1
the resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the semiconductor substrate and the second electrode, and a second region that has a second electrical resistivity higher than the first electrical resistivity of the first region
Data Source
AI summary
A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.