Semiconductor Resistance Stabilization via Dielectric Isolation
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Solution Overview
Problem
Resistance elements in semiconductor integrated circuits face variations in resistance value due to substrate potential and power supply voltage fluctuations, affecting their stability and electrical characteristics.
Innovation Solution
The semiconductor device incorporates first and second wells formed as impurity diffusion regions in the substrate, with an intermediate dielectric film and a conductive layer held at a potential to prevent inversion layer formation and current leakage, stabilizing the resistance elements by distancing them from the substrate and resistive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If resistance elements are formed with thin oxide film and close proximity to polysilicon layer, then manufacturing precision is improved, but electrical characteristics become unstable due to substrate potential and power supply voltage variations
Solution Approach 1:
A thick intermediate dielectric film (500-2000 nm) is introduced between the conductive layer and the semiconductor substrate to electrically isolate the resistance elements from substrate potential variations. This intermediary layer acts as a buffer that prevents direct electrical interaction, thereby stabilizing resistance characteristics while maintaining the close-proximity structure for manufacturing precision.
Solution Approach 2:
The patent increases the thickness of the intermediate dielectric film in the vertical dimension to achieve electrical isolation, rather than changing the lateral positioning. This dimensional approach allows the resistance elements to remain close to the substrate for manufacturing precision while the thick dielectric layer provides the necessary electrical stability by increasing the isolation distance vertically.
2Device complexity
If conductive layer is placed close to resistance elements, then device complexity is reduced, but current leakage occurs due to inversion layer formation
Solution Approach 1:
The patent changes the thickness parameter of the intermediate dielectric film to 500-2000 nm, which is sufficiently thick to prevent inversion layer formation and current leakage. By adjusting this critical dimension parameter, the design maintains structural simplicity with a single conductive layer while eliminating the harmful leakage effect through optimized dielectric thickness.
3Manufacturing precision
If resistance elements are positioned close to substrate, then manufacturing precision is improved, but resistance value variations increase due to substrate potential fluctuations
Solution Approach 1:
The thick intermediate dielectric film serves as an intermediary barrier that electrically isolates the resistance elements from substrate potential fluctuations. This allows the resistance elements to be positioned close to the substrate for manufacturing precision while the dielectric layer prevents electrical coupling that would cause resistance value variations.
Solution Approach 2:
The conductive layer held at a fixed potential (e.g., power supply voltage) creates an equipotential region above the intermediate dielectric film. This equipotential structure shields the resistance elements from substrate potential variations, ensuring consistent resistance values while maintaining close positioning for manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the stability and reduces variations in resistance characteristics, effectively preventing current leakage and maintaining precise voltage control in analog integrated circuits.
Implementation Method 1
A conductive layer formed above a semiconductor region between mutually adjacent wells is held at a power supply voltage to block the effects of electric fields created by higher layers of wiring and prevent the formation of p-type inversion layers
Implementation Method 2
An intermediate dielectric film formed on the semiconductor substrate intervenes between the conductive layer and the semiconductor region
Implementation Method 3
The diffused resistance regions 103 are formed by implantation of impurity ions such as boron ions into the silicon substrate 101 through the thin oxide film 121
Data Source
AI summary
A semiconductor device includes first and second wells formed side by side as impurity diffusion regions of a first conductive type in a semiconductor substrate, below an intermediate dielectric film that covers a major surface of the substrate. A conductive layer formed above the intermediate dielectric film is held at a potential. A first resistive layer is formed on the intermediate dielectric film and is electrically connected to the first well. A second resistive layer is formed on the intermediate dielectric film and is electrically connected to the second well. The first resistive layer and first well form a first resistance element. The second resistive layer and second well form a second resistance element.