Semiconductor Device with Local Resistance Control for Display Wiring
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Solution Overview
Problem
As display devices trend towards larger screens and higher resolutions, the increase in screen size or definition leads to higher wiring resistance in the display portion, which existing technologies struggle to effectively mitigate.
Innovation Solution
A semiconductor device is designed with a specific layered structure, including a semiconductor layer, insulating layers, a metal oxide layer, and a conductive layer, where the end portions of the insulating and metal oxide layers are positioned inward from the semiconductor layer, and the third insulating layer covers the top and side surfaces of the semiconductor and conductive layers, to manage electrical resistance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the screen size or resolution is increased, then the display performance is improved, but the wiring resistance in the display portion increases
Solution Approach 1:
The patent applies local quality by creating distinct regions within the semiconductor layer with different resistance characteristics. Specifically, it forms a low-resistance region in the source/drain areas and maintains higher resistance in the channel region, thereby locally optimizing electrical properties to reduce overall wiring resistance while preserving display performance
Solution Approach 2:
The patent utilizes parameter changes by modifying the resistance characteristics of the semiconductor layer through controlled formation of low-resistance regions. By adjusting the resistance parameter in specific areas (source/drain versus channel), the patent achieves reduced wiring resistance without compromising the display portion's performance
Data Source
AI summary
A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.