Semiconductor Resistive Field Plate Vertical Stacking
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Solution Overview
Problem
High voltage integrated circuits with resistive field plates face high leakage current issues, leading to increased power consumption, and existing solutions that increase resistance by extending the field plate length result in larger semiconductor chip sizes, reducing chip yield and increasing costs.
Innovation Solution
A semiconductor device design where a resistive element is formed by alternately connecting and disposing diffusion resistance regions and thin film resistance layers in series and parallel across an insulating film, effectively increasing resistance without expanding the chip size by using a spiral planar pattern that doubles the effective length while maintaining a constant array width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the number of turns of the resistive field plate is increased to increase the total resistance value, then the leakage current is reduced, but the planar size and chip size increase
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional vertical structure by stacking multiple resistive field plates in the thickness direction. This allows increasing the total resistance value through vertical stacking rather than horizontal expansion, thereby reducing leakage current without increasing chip area. The insulating film between stacked plates provides electrical isolation while maintaining compact footprint.
Solution Approach 2:
The patent embeds multiple resistive field plates within a vertical stack configuration, where each plate is nested above the other separated by insulating films. This nested arrangement maximizes the use of vertical space to achieve higher total resistance without occupying additional planar area, effectively reducing leakage current while maintaining compact chip size.
2Loss of energy
If the effective length of the resistive field plate is increased to increase resistance, then the leakage current is reduced, but the chip acquisition rate decreases and cost increases
Solution Approach 1:
The patent increases the effective length of the resistive field plate by stacking multiple plates vertically in the thickness direction rather than extending them horizontally. This vertical stacking approach increases the total resistance value and reduces leakage current while maintaining a compact planar footprint, thereby preserving high chip acquisition rates and reducing costs.
3Reliability
If a resistive field plate is used instead of a capacitive field plate, then the coercive force of potential is strong and reliability is high, but the leakage current increases and power consumption increases
Solution Approach 1:
The patent divides a single resistive field plate into multiple segmented plates stacked vertically, with each plate contributing to the total resistance value. By stacking multiple segments, the total resistance increases, which reduces leakage current while maintaining the high coercive force of potential characteristic of resistive field plates, thus achieving both high reliability and low power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces leakage current and power consumption while maintaining a compact chip size, achieving stable breakdown voltage and efficient voltage distribution through a pseudo double RESURF structure.
Implementation Method 1
a resistive element is configured wherein diffusion resistance regions (17j, 17j+1, and 17j+2) provided in an upper portion of a semiconductor base (1), and thin film resistance layers (16j, 16j+1, and 16j+2) isolated and distanced from the semiconductor base (1) and diffusion resistance regions (17j, 17j+1, and 17j+2) across insulating films (14, 15) are alternately connected in series and alternately disposed in parallel
Implementation Method 2
thin film resistance layers (16j, 16j+1, and 16j+2) isolated and distanced from the semiconductor base (1) and diffusion resistance regions (17j, 17j+1, and 17j+2) across insulating films (14, 15)
Implementation Method 3
As the capacitive field plate or resistive field plate has a function of relaxing electrical field concentration in a depletion layer of a semiconductor surface, high breakdown voltage can be stably secured
Data Source
AI summary
A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.