Semiconductor Resistive Layer Vertical Integration
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Solution Overview
Problem
In semiconductor devices, the layout of resistive layers occupies significant area, limiting the density of transistors and increasing the cost of advanced semiconductor processes, particularly in smaller geometry sizes like the 7-nanometer (N7) or 5-nanometer (N5) processes.
Innovation Solution
The resistive layer is disposed between intermediate conductive layers, specifically between the third conductive layer and the topmost conductive layer, creating space for additional transistors and optimizing area usage, and at least one conductive layer is floated over or under the resistive layer to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistors are added to reduce noise and minimize faster etching, then electrical performance is improved, but area occupied increases by 5% or more of the analog area
Solution Approach 1:
The patent moves resistors from the planar layout to the vertical dimension by forming them within conductive layers stacked above transistor regions. This three-dimensional integration allows resistors to occupy vertical space rather than horizontal space, reducing their footprint in the analog area while maintaining their electrical performance function.
Solution Approach 2:
The patent embeds resistors within the conductive layer structure that already exists for transistor interconnection. The resistors are formed in conjunction with the conductive layers, effectively nesting the resistor function within the existing interconnect architecture rather than adding separate dedicated resistor structures.
2Productivity
If geometry size is scaled down to increase functional density, then productivity is improved, but area occupied by resistors becomes more significant
Solution Approach 1:
By forming resistors in vertical conductive layers above the transistor plane, the patent enables continued scaling of transistor geometry without proportionally increasing resistor area. The vertical stacking allows functional density to increase through the third dimension while keeping the planar footprint compact.
Solution Approach 2:
The conductive layers serve multiple functions: they provide interconnection between transistors and simultaneously host resistor structures. This multi-functionality reduces the need for separate dedicated resistor areas, enabling better area utilization as devices are scaled to smaller geometries.
3Reliability
If resistors occupy significant area, then noise reduction is achieved, but transistor density is limited
Solution Approach 1:
The patent resolves the trade-off between noise reduction and transistor density by placing resistors in the vertical dimension within conductive layers. This allows sufficient resistor material to be present for noise reduction while the horizontal space remains available for higher transistor density.
Solution Approach 2:
The patent segments the die into different vertical zones: transistors in the lower plane and resistors in the upper conductive layers. This spatial segmentation allows both high-density transistor placement and adequate resistor material for noise reduction to coexist without competing for the same planar space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more efficient area cost by enabling more transistors in the same die size or reducing die size while enhancing electrical performance by minimizing parasitic capacitance.
Implementation Method 1
at least one conductive layer is floated over or under the resistive layer to reduce parasitic capacitance
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.