Semiconductor Resistor Using Gate Stack Conductive Layers
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Solution Overview
Problem
Conventional semiconductor manufacturing processes result in resistors with low resistance values, especially when using high conductivity materials, which is undesirable in certain applications.
Innovation Solution
The integration of a gate stacked structure with a dielectric layer, a first conductive layer, and a second conductive layer, where the first conductive layer forms the resistor body and the second conductive layer acts as resistor terminals, with the first conductive layer having a thickness of 10 Å to 100 Å and a width of 1 nm to 10 nm, and the use of high-K dielectric materials like HfO2 for increased resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a high conductivity material is used for the resistor body, then the ease of manufacture is improved, but the resistance value becomes too low
Solution Approach 1:
The patent changes the physical parameters of the resistor structure by reducing the thickness and width of the first conductive layer to achieve high resistance values. By controlling the dimensions (thickness: 10-100 Å, width: 1-10 nm) of the conductive layer, the resistance can be increased without changing the material composition, thus maintaining ease of manufacture while achieving the desired resistance value.
Solution Approach 2:
The patent transitions from controlling resistance through material selection to controlling it through dimensional parameters. By moving to a nanoscale thickness and width regime, the resistance value is controlled in the dimensional domain rather than the material composition domain, allowing high conductivity materials to be used while achieving high resistance values.
2Ease of manufacture
If the cross-sectional area of the resistor body is increased, then the ease of manufacture is improved, but the resistance value decreases
Solution Approach 1:
The patent explicitly controls the cross-sectional area parameters (thickness and width) of the first conductive layer to achieve the desired resistance value. By setting thickness to 10-100 Å and width to 1-10 nm, the cross-sectional area is optimized to provide high resistance while maintaining manufacturability through standard semiconductor fabrication processes.
Data Source
AI summary
An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.