Semiconductor Resistor Metal Gate Integration
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Solution Overview
Problem
In semiconductor devices, the reduction in gate structure dimension and gate insulation layer thickness leads to leakage current issues, and the use of high-k materials can cause Fermi-level pinning, increasing threshold voltage and affecting device performance, especially when integrating metal gates with resistors in scaled-down designs.
Innovation Solution
A semiconductor structure and method where a resistor is formed without a metal layer, using a polysilicon layer for current flow, and a metal gate structure is created using a high-k dielectric layer and polysilicon, with a salicide block mask process that reuses existing masks to remove the metal layer in the resistor area, avoiding performance degradation and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is used in the resistor to reduce resistance, then the resistance of the device is reduced, but the metal layer deviates the performance of the resistor and causes Fermi-level pinning when integrated with high-k materials
Solution Approach 1:
The patent extracts and removes the metal layer from the resistor structure, keeping only the polysilicon layer to form the resistor. This eliminates the harmful interaction between metal and high-k dielectric materials that causes Fermi-level pinning, while maintaining the resistor's functional performance through the polysilicon layer alone
Solution Approach 2:
The patent applies different material compositions to different regions: the resistor region uses only polysilicon without metal layer to avoid Fermi-level pinning, while the gate region retains the metal layer for optimal gate performance. This localized differentiation resolves the contradiction by allowing each component to have its optimal structure
2Length of moving object
If the gate insulation layer thickness is reduced to scale down device dimension, then the device dimension is reduced, but leakage current increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulation layer from standard silicon oxide (k≈3.9) to high-k materials (k>25). This parameter change allows the physical thickness to be reduced for scaling while maintaining sufficient electrical insulation, thereby reducing leakage current despite the thinner physical layer
3Object-generated harmful factors
If a high-k material is used to replace silicon oxide for forming the gate insulation layer to reduce leakage current, then leakage current is reduced, but the threshold voltage is increased due to Fermi-level pinning
Solution Approach 1:
The patent removes the polysilicon gate layer that interacts with the high-k dielectric, eliminating the source of Fermi-level pinning. By using a metal gate instead of polysilicon gate, the harmful interaction is extracted from the system while retaining the benefits of high-k materials for leakage current reduction
4Reliability
If an extra mask is added to remove the metal layer in the resistor area, then the resistor performance is improved, but the fabrication complexity and cost increase
Solution Approach 1:
The patent merges the metal layer removal step for the resistor with the existing salicide block mask process. The same mask pattern serves dual purposes: blocking salicide formation in resistor areas and defining the metal layer removal pattern. This consolidation eliminates the need for an extra dedicated mask while achieving the desired resistor performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains resistor performance by eliminating metal layer resistance and reduces fabrication costs by using existing masks, enhancing device performance and competitiveness.
Implementation Method 1
a high dielectric constant (high-k) material is used to replace silicon oxide for forming the gate insulation layer
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.