Semiconductor Resistor Stability via Recessed Isolation
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Solution Overview
Problem
In semiconductor devices, resistors with predictable and stable resistance values are challenging to fabricate due to variations caused by silicidation and metallization processes, as well as heat exposure, which affect the resistivity of materials like CoSix and NiSix, and metal layers during fabrication.
Innovation Solution
The solution involves forming resistors in a semiconductor device with a recessed isolating structure in the substrate, ensuring they are not silicidized or metallized, and minimizing heat exposure to maintain consistent resistance values. This is achieved by recessing the isolating structures below the substrate surface and embedding the resistors in an insulating layer, preventing changes during silicidation or metallization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If silicide materials (CoSix, NiSix) or metal gate materials (W, Cu, Al) are used to form resistors with lower resistance, then the resistance value decreases, but the resistivity becomes highly susceptible to heat and thickness variations during fabrication
Solution Approach 1:
The patent introduces an intermediary protective layer (such as silicon nitride or silicon oxide) between the resistor and the surrounding environment. This protective layer acts as a barrier that prevents direct exposure to heat and physical processes during fabrication, thereby stabilizing the resistivity while allowing the use of low-resistance materials. The protective layer mediates the interaction between the resistor and harmful fabrication conditions.
Solution Approach 2:
The patent employs parameter changes by carefully controlling the thickness of the resistor layer and the protective layer, as well as adjusting fabrication parameters such as deposition temperature and annealing conditions. By optimizing these parameters, the patent achieves stable resistivity values despite using materials that are inherently sensitive to process variations.
2Manufacturing precision
If chemical-mechanical polishing (CMP) is applied to metallize gate patterns, then the metal layer thickness can be controlled, but dishing of the resistor material occurs which greatly changes the resistance value
Solution Approach 1:
The protective layer serves as an intermediary that shields the resistor from the mechanical action of CMP polishing. During the metallization process, the CMP tool removes material from exposed surfaces, but the protective layer prevents direct contact with the resistor, thereby preventing dishing while allowing precise thickness control of the metal gate layers.
Solution Approach 2:
The patent segments the device structure into distinct regions: the resistor region protected by the protective layer, and the gate region subjected to CMP processing. This segmentation allows different fabrication processes to be applied to different parts of the device independently, enabling precise metal layer control in gate regions without affecting resistor integrity.
3Quantity of substance
If silicidation processes are applied to gate patterns to reduce resistance, then the gate resistance decreases, but the resistor resistance value changes due to heat and material interaction
Solution Approach 1:
The protective layer acts as a thermal and chemical barrier during silicidation processes. It prevents silicon from diffusing into the resistor and blocks heat transfer that would otherwise alter the resistor's crystalline structure and resistivity. This intermediary protection allows aggressive silicidation processes to be applied to gates without compromising resistor performance.
Solution Approach 2:
The patent extracts the resistor from the active fabrication zones by covering it with the protective layer. This extraction removes the resistor from the harmful environment where silicidation and other high-temperature processes occur, allowing gate optimization without resistor degradation.
Data Source
AI summary
In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.