Semiconductor Device Resistor Integration via Vertical Overlap
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of semiconductor devices is limited due to the large area occupied by the resistance element region, which requires separate spaces for resistors and transistors, hindering the miniaturization and efficiency of 3D semiconductor devices.
Innovation Solution
The semiconductor device is designed with resistance elements formed within recess regions in the substrate, overlapping with peripheral circuit and contact regions, eliminating the need for separate space and allowing for high integration by alternately stacking material layers and forming interlayer insulation layers to create recess regions for resistor placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If resistors are formed in a separate resistance element region, then the resistor implementation is simple, but the area occupied is large which limits integration
Solution Approach 1:
The patent merges the resistance element region with the peripheral circuit region, allowing resistors to be formed within the same region as transistors. This is achieved by forming a resistor through a doped polysilicon layer that overlaps with the transistor gate, eliminating the need for a separate resistance element region and reducing overall device area.
Solution Approach 2:
The patent transitions from a planar arrangement where resistors and transistors occupy separate 2D regions to a 3D overlapping structure. The resistor is formed by a polysilicon layer that overlaps with the transistor gate in the vertical dimension, allowing both components to coexist in the same footprint area and improving integration density.
2Adaptability or versatility
If multiple resistors are formed in the resistance element region, then the circuit functionality is improved, but the area of the resistance element region increases
Solution Approach 1:
The patent enables multiple resistors to be formed in a compact area by utilizing vertical stacking and overlapping. Different resistors can be formed at different vertical levels or by overlapping polysilicon layers, allowing multiple resistance elements to share the same footprint area and maintain circuit functionality without proportionally increasing device area.
3Ease of manufacture
If resistors and transistors are arranged in different regions, then the formation process is simplified, but the overall device area increases
Solution Approach 1:
The patent combines the formation of resistors and transistors in the same peripheral circuit region. The resistor is formed using the same doped polysilicon layer that forms the transistor gate, allowing both components to be manufactured simultaneously in the same region without requiring separate processing steps or regions, thus reducing overall device area while maintaining manufacturing simplicity.
Data Source
AI summary
Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate.