Semiconductor Rewiring Structure for Pad Misalignment and Short-Circuit Risk
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Solution Overview
Problem
Existing semiconductor fabrication technologies result in low yield due to misalignment and insufficient exposure of pads, leading to invalid electrical connections and short circuits in the redistribution layer.
Innovation Solution
A method involving the formation of a conductive film layer with varying thicknesses, where the layer on the insulating layer facing away from the chip is thinner than on the pads, ensuring direct contact and avoiding misalignment by not broadening the openings in the insulating layer, thus maintaining electrical connection and reducing the distance between adjacent wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a patterned photoresist layer is formed with hollow regions to expose pads, then electrical connection between conductive structures and pads can be achieved, but opening misalignment caused by process errors may lead to insufficient exposure of pads and invalid electrical connection
Solution Approach 1:
The patent changes the thickness parameter of the conductive film layer, making it non-uniform: thicker over the pads and thinner over the insulating layer. This parameter variation ensures that during etching, the conductive structures are formed with sufficient thickness to maintain reliable electrical contact with the pads, while the thinner portions are completely etched away. This resolves the alignment issue by making the connection reliability dependent on thickness rather than precise lateral positioning.
2Reliability
If the hollow regions of the photoresist layer are broadened to ensure full exposure of pads considering process errors, then electrical connection is guaranteed, but short circuit between adjacent wirings occurs due to insufficient distance between hollow regions
Solution Approach 1:
The patent applies local quality by creating spatially varying thickness in the conductive film layer. The layer is locally thicker over the pad regions to ensure reliable electrical connection, and locally thinner over the insulating layer regions to prevent short circuits between adjacent structures. This local differentiation allows the openings to maintain their original dimensions without broadening, thus avoiding short circuits while ensuring adequate electrical connection through the thicker portions.
3Reliability
If openings in the insulating layer are broadened to ensure pad exposure, then electrical connection reliability improves, but distance between adjacent wirings decreases leading to short circuit risk
Solution Approach 1:
The patent transitions from a two-dimensional lateral dimension problem to a three-dimensional solution by utilizing the vertical thickness dimension. Instead of broadening the openings laterally (which would reduce wiring spacing), the conductive film layer is made thicker in the vertical dimension over the pad regions. This allows the openings to remain narrow, maintaining adequate distance between adjacent wirings, while the increased vertical thickness ensures sufficient electrical connection reliability.
Data Source
AI summary
The present application provides a fabrication method for a semiconductor structure and a semiconductor structure. The fabrication method comprises: providing a structure to be wired, the structure comprising at least one chip, the chip having a front surface, and the front surface of the chip being provided with a plurality of solder pads; forming a first insulating layer on the front surface of the chip, the first insulating layer being provided with a plurality of openings, and each opening exposing at least part of one solder pad; forming a conductive film layer on the side of the first insulating layer distant from the chip; removing the part of the conductive film layer that exceeds the first insulating layer; and forming a rewiring structure on the side of the first insulating layer distant from the chip.