Semiconductor RF Antenna Resonance via Packaging Substrate Integration
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Solution Overview
Problem
Semiconductor devices with internal antennas for RF communication face challenges in achieving adequate performance due to their small size, leading to limited communication range and increased manufacturing costs, as existing antenna designs struggle to resonate effectively within the constraints of native processing steps.
Innovation Solution
The integration of an RF structure with a semiconductor chip featuring an RF core, chip pads, and an antenna formed of wire or printed conductors, which surrounds the primary element, allowing for resonance at desired frequencies without requiring additional manufacturing steps, thus enabling efficient RF communication within the native processing framework.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If internal antennas are made small to fit within semiconductor devices, then device integration is improved, but RF communication range and performance deteriorate
Solution Approach 1:
The patent extends the antenna structure from the chip surface into the packaging substrate, utilizing the third dimension (depth) to increase antenna length and improve RF performance without increasing the chip footprint. The antenna conductor traces are formed to extend beyond the chip edges and into the packaging material, effectively using vertical space to resolve the size-performance contradiction.
Solution Approach 2:
The antenna structure is nested within the packaging substrate, with the antenna conductor traces being embedded in the packaging material surrounding the chip. This nesting approach allows the antenna to utilize the packaging volume as part of its resonant structure, achieving longer effective antenna length within the compact packaged device form factor.
2Reliability
If off-tag antennas are used to improve RF communication range, then communication performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the antenna fabrication process with the native semiconductor packaging process. The antenna conductor traces are formed using the same printing or deposition techniques already used for creating electrical interconnections in the package, eliminating the need for separate antenna manufacturing steps and reducing overall manufacturing complexity.
Solution Approach 2:
The packaging substrate serves dual functions: it provides mechanical support and electrical interconnection for the chip, and simultaneously serves as the medium in which the antenna traces are formed. This multi-functionality eliminates the need for dedicated antenna components and simplifies the overall manufacturing process.
3Reliability
If antenna traces are extended beyond chip edges into packaging, then antenna resonance performance is improved, but chip area available for primary functions is reduced
Solution Approach 1:
The antenna structure transitions from being confined to the two-dimensional chip surface to extending into the three-dimensional packaging volume. By utilizing the depth dimension and forming antenna traces in the packaging substrate rather than on the chip itself, the invention achieves longer antenna paths without consuming valuable chip real estate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved RF communication performance by optimizing antenna design within the semiconductor structure, enhancing communication range and reducing manufacturing costs by leveraging native processing steps, while maintaining the primary function of the semiconductor device.
Implementation Method 1
allowing for resonance at desired frequencies
Data Source
AI summary
A RF structure including a semiconductor chip with an RF element having an RF core with two electrically connected chip pads, including a chip carrier having two carrier pads connected to the two chip pads and including an antenna connected to the carrier pads and electrically connected to the chip pads and to the RF core. The antenna is formed of wires, printed conductors, seal rings or other structures on, below or above the top plane of the semiconductor chip. A primary element is provided where the RF element is a secondary element. The primary element occupies a primary region and the RF core of the secondary element occupies a secondary region where the secondary region is much smaller than the primary region. The RF core secondary region is formed with the same native processing as used for the primary element.