Semiconductor Package Rigid Support Blocks Prevent Thermal Deviation

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Solution Overview

Problem

The existing wafer-level semiconductor packaging methods face issues with positional deviations of semiconductor elements due to thermal expansion of thermal release tapes, leading to poor electrical connections and low product yield, especially as carrier sizes increase.

Innovation Solution

A semiconductor package and fabrication method where connection units are formed only on specific chip areas, using an insulating layer and a circuit layer to ensure accurate positioning and electrical connectivity, with the insulating layer made of silicon dioxide or silicon nitride, and a dielectric layer for encapsulation, preventing thermal expansion and contraction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If thermal release tape is used to support semiconductor elements during molding, then the molding process can be performed, but positional deviations of semiconductor elements occur due to thermal expansion

Engineering Contradiction:
Improvemolding processVSAvoidpositioning accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the carrier into multiple rigid support blocks positioned at specific locations, rather than using a continuous flexible thermal release tape. This segmentation provides discrete, stable support points that prevent thermal expansion-related positioning errors while still enabling the molding process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces rigid support blocks as intermediary structures between the carrier and semiconductor elements. These support blocks serve as stable mediators that maintain precise positioning during molding, replacing the problematic thermal release tape that caused expansion and positioning deviations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If carrier size is increased, then more chip areas can be processed, but positional deviation of semiconductor elements increases

Engineering Contradiction:
Improvecarrier areaVSAvoidpositioning accuracy
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent uses multiple discrete rigid support blocks distributed across the carrier surface, allowing the carrier to be enlarged for processing more chips while maintaining positioning accuracy at each support point. The segmented support structure prevents the cumulative positioning errors that would occur with a single large-scale support system.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If thermal release tape is heated during molding, then the molding process can proceed, but the tape loses adhesive property and causes positional deviations

Engineering Contradiction:
Improvemolding processVSAvoidelectrical connection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses rigid support blocks that can be easily removed after molding, replacing the thermal release tape that loses its adhesive properties when heated. These support blocks serve their purpose during molding and are then discarded or removed, avoiding the reliability issues caused by heated adhesive loss.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS9041189B2Semiconductor package and method of fabricating the same
Publication Date: 2015.05.26 SILICONWARE PRECISION IND CO LTD
  • US9041189B2 patent drawing
  • US9041189B2 patent drawing
  • US9041189B2 patent drawing

AI summary

A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.