Semiconductor Ring Structure Alignment for Source/Drain Leakage Control
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Solution Overview
Problem
As semiconductor memory devices become smaller, the alignment between elements on different layers becomes increasingly difficult, leading to challenges in the semiconductor process, particularly in achieving precise alignment of conductive layers with source/drain regions.
Innovation Solution
A method is developed where a spacer is formed on the sidewalls of a trench above a contact plug, allowing for the formation of a ring structure in the patterned conductive layer that aligns with the source/drain region, enabling corresponding alignment of other elements and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of the semiconductor memory device is reduced to increase integration, then more functional devices can be integrated on the same chip and the electronic product becomes more compact, but the alignment between elements on different layers becomes increasingly difficult
Solution Approach 1:
The patent introduces a ring structure as an intermediary alignment feature between the contact plug and the source/drain region. This ring structure serves as a mediator that facilitates precise alignment during the patterning process, enabling accurate positioning of conductive layers relative to underlying transistor elements even at reduced critical dimensions
Solution Approach 2:
The ring structure is formed in advance before the final conductive layer patterning. This preliminary alignment feature is created using spacer formation and photoresist patterning steps that establish precise geometric relationships ahead of time, allowing subsequent layers to be aligned to this pre-established reference structure
2Volume of moving object
If the critical dimension of the device gets smaller, then the electronic product may be more compact, but semiconductor process techniques face many challenges including alignment difficulties
Solution Approach 1:
The patent segments the patterning process into multiple distinct steps: forming the ring structure, forming spacers, applying photoresist layers, and selective etching. This segmentation of the complex patterning process into manageable stages allows for better control and alignment at each step, reducing the overall process complexity despite the small device dimensions
3Ease of manufacture
If alignment between layers is not precise, then manufacturing becomes easier, but current leakage increases and performance deteriorates
Solution Approach 1:
The ring structure and spacer formation create a self-aligning mechanism where the geometry of previously formed structures automatically defines the position of subsequent features. The spacer width, for example, self-determines the distance between the ring structure and the contact plug, reducing reliance on external alignment processes and ensuring consistent alignment that prevents current leakage
Data Source
AI summary
A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.