Semiconductor Device Rising Portion Spacing
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Solution Overview
Problem
Conventional semiconductor devices experience strain and potential cracking at the upper-surface electrode due to thermal expansion of metal connecting plates, which are sealed with resin, leading to increased stress at the triple junctions between the electrode, plated film, and gate runner.
Innovation Solution
The semiconductor device design includes a metal connecting plate with a rising portion that maintains a minimum distance of 1 mm from gate runners and guard rings, and a curved boundary portion to reduce strain, preventing solder intrusion and minimizing stress on the upper-surface electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal connecting plate is sealed with resin, then the device is protected and sealed, but the rising portion presses the upper-surface electrode causing strain and potential cracks
Solution Approach 1:
The patent introduces a horizontal distance dimension between the rising portion and gate runner to solve the vertical pressing problem. By positioning the rising portion at least 1 mm horizontally away from the gate runner, the design transfers the problem from vertical stress management to horizontal spatial arrangement, preventing strain concentration at the triple junction while maintaining sealing integrity.
2Reliability
If the insulating film of the gate runner contracts, then a gap is generated allowing solder intrusion, but increasing distance prevents this while potentially affecting electrical connection
Solution Approach 1:
The patent introduces a curved portion with radius of curvature of at least 1 mm as an intermediary geometric feature between the rising portion and gate runner. This curved boundary acts as a mediator that prevents solder intrusion into gaps while maintaining adequate electrical connection, transforming the sharp corner into a gradual transition that manages both sealing and conductivity requirements.
3Volume of moving object
If the rising portion is positioned close to the gate runner, then the device structure is compact, but strain concentration occurs at the triple junction
Solution Approach 1:
The patent applies local quality by creating a differentiated spatial relationship: the rising portion is positioned at least 1 mm away from the gate runner horizontally, while maintaining close proximity elsewhere. This localized spatial arrangement reduces strain at the critical triple junction area without significantly increasing overall device volume, allowing compact design with stress management.
4Strength
If a curved portion with large radius of curvature is provided, then strain is reduced at the boundary, but manufacturing complexity increases
Solution Approach 1:
The patent specifies a quantitative parameter threshold (radius of curvature of at least 1 mm) for the curved portion at the rising portion boundary. This parameter-based approach balances strain reduction with manufacturing feasibility, providing a clear design criterion that reduces stress concentration while remaining practical for fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces strain at the triple junctions, preventing cracks and extending the lifespan of the semiconductor device by ensuring adequate distance between the rising portion and gate runners and guard rings, while allowing for efficient solder reflow and reduced thermal expansion impact.
Implementation Method 1
If the temperature of the metal connecting plate varies, a rising portion of the metal connecting plate tries to expand or contract in the upward and downward directions
Data Source
AI summary
A semiconductor device includes: an upper-surface electrode on an upper surface of a semiconductor element; a plated layer on an upper surface of the upper-surface electrode; gate runners penetrating the plated layer and formed to extend above the upper surface of the semiconductor element; and a metal connecting plate arranged above the plated layer and electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion at an end of the joint portion, the rising portion extending in a direction away from the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, a first distance, which is a shortest distance between the rising portion and the gate runner not intersecting the rising portion, is equal to or longer than 1 mm.