Semiconductor Routing Structure Alignment for Congestion Reduction
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Solution Overview
Problem
In high-density integrated circuit design, the connection of input/output terminals between adjacent standard cells through upper metal layers leads to congestion and DRC violations, as existing methods do not allow for direct alignment of conductive patterns within the same metal layer, necessitating the use of routing resources from higher layers.
Innovation Solution
The method involves rearranging conductive patterns and segments within the same metal layer to enable direct electrical connections between adjacent cells, allowing for alignment and connection without relying on upper metal layer routing, thus freeing up routing resources and reducing external routing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If input/output terminals of adjacent standard cells are connected through upper metal layers, then electrical connection between cells is achieved, but routing congestion occurs and DRC violations arise in high density design
Solution Approach 1:
The patent transitions from using upper metal layers (vertical dimension) for routing to using the same metal layer as the pin shape (horizontal dimension). This dimensional shift allows direct local connections between adjacent cells without consuming routing resources in upper layers, thereby reducing routing congestion while maintaining electrical connectivity.
2Reliability
If upper metal layer routing resources are used for connecting adjacent cells, then electrical connection is established, but routing resources become scarce and DRC violations occur
Solution Approach 1:
The patent extracts the routing function from upper metal layers and implements it directly in the same metal layer as the pin shape. This extraction frees up upper metal layer routing resources for other critical connections, preventing resource scarcity and DRC violations while maintaining necessary electrical connections between adjacent cells.
3Productivity
If local direct connection is implemented using the same metal layer as pin shape, then routing resources in upper layers are freed, but conductive patterns must be precisely aligned between adjacent cells
Solution Approach 1:
The patent performs preliminary alignment of conductive patterns between adjacent cells during the design and fabrication process. By pre-positioning the conductive patterns in the same metal layer as the pin shape and ensuring their alignment before final assembly, the method enables precise local direct connections without requiring complex post-processing or upper layer routing, thus freeing routing resources while achieving the necessary manufacturing precision.
Data Source
AI summary
The present disclosure provides a method and an apparatus for generating a layout of a semiconductor device. The method includes placing a first cell and a second cell adjacent to the first cell, placing a first conductive pattern in a first track of the first cell extending in a first direction, wherein the first conductive pattern is configured as an input terminal or an output terminal of the first cell, placing a second conductive pattern in a first track of the second cell extending in the first direction, wherein the second conductive pattern is configured as an input terminal or an output terminal of the second cell, and aligning the first conductive pattern with the second conductive pattern.