Semiconductor Routing Grid Alignment for Via Placement
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Solution Overview
Problem
In multi-level interconnect technologies for semiconductor integrated circuits, the misalignment of grid points between orthogonal and diagonal interconnects leads to complications in via hole placement, especially at reduced wire widths, increasing design complexity and restricting placement positions.
Innovation Solution
A computer automated design system and method that aligns grid areas and diagonal grid areas across multiple wiring layers, ensuring overlap and matching grid points to facilitate efficient routing of wires and reduce crosstalk, thereby allowing for proper via hole placement without displacement issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If diagonal interconnect technology is used to reduce wire length and crosstalk, then wiring area is reduced and power consumption decreases, but grid point misalignment between orthogonal and diagonal layers occurs, complicating via hole placement
Solution Approach 1:
The patent introduces a fourth wiring layer to resolve the grid point misalignment problem. By adding this additional dimension (layer), the design can accommodate both orthogonal and diagonal interconnects without forcing via holes to be placed at non-grid point positions, thus maintaining routing efficiency while avoiding placement complexity
Solution Approach 2:
The patent segments the wiring structure into distinct orthogonal and diagonal interconnect regions with separate grid systems. Each region maintains its own grid alignment, allowing via holes to be placed at proper grid points within each segment while preserving the benefits of both interconnect types
2Quantity of substance
If wire width is reduced to increase integration density, then more wires can be packed, but grid point misalignment becomes more obvious, further complicating via hole placement
Solution Approach 1:
By introducing the fourth wiring layer, the patent provides an additional dimensional space that allows via holes to be placed at proper grid points even when wire widths are reduced. This extra layer acts as a buffer that resolves the precision issue without compromising integration density
3Object-affected harmful factors
If diagonal interconnect is used to magnify pitch and reduce crosstalk, then signal interference decreases, but the design process becomes more complicated due to grid point displacement restrictions
Solution Approach 1:
The fourth wiring layer provides an additional dimensional solution that allows the design to maintain diagonal interconnect benefits for crosstalk reduction while eliminating the need to navigate complex grid point displacement restrictions, as vias can be placed at proper grid points in the expanded layer structure
Solution Approach 2:
By segmenting the design into orthogonal and diagonal regions with independent grid systems, the patent allows each region to optimize for crosstalk reduction while the overall structure manages placement complexity through clear regional boundaries
Data Source
AI summary
A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a next routing module configured to set a second grid area and a second diagonal grid area and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire.