Semiconductor Memory Row-Hammer Control With Short Internal Writes
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face issues with data loss due to leakage currents and performance degradation from frequent word-line transitions, leading to increased refresh operations and power consumption, especially in high-capacity systems.
Innovation Solution
Implementing a row hammer management circuit that counts access frequencies to memory cell rows, performs internal read-update-write operations, and uses higher power supply voltages for write operations during reduced time intervals to mitigate performance degradation and reduce refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequent word-line transitions are performed to access memory cells intensively, then data access speed is improved, but cell charges are lost due to leakage current and performance degradation occurs
Solution Approach 1:
The patent performs preliminary detection of row access frequencies using a row hammer detection circuit before significant data loss occurs. When excessive access frequency is detected, the system proactively performs refresh operations on adjacent memory cells to prevent charge leakage and data loss, rather than waiting for errors to occur.
Solution Approach 2:
The patent implements a feedback mechanism where the row hammer detection circuit continuously monitors word-line access frequencies and provides feedback signals to control the refresh operation timing. This closed-loop control adjusts refresh operations based on actual access patterns, optimizing the balance between data retention and access performance.
2Reliability
If refresh operations are performed frequently to prevent data loss, then data retention is improved, but power consumption increases
Solution Approach 1:
The system performs refresh operations only when row hammer conditions are detected or anticipated, rather than continuously refreshing all memory rows. This selective refresh approach maintains data retention while significantly reducing unnecessary refresh operations and associated power consumption.
Solution Approach 2:
The patent dynamically changes refresh operation parameters based on detected access patterns. When high-frequency access to certain rows is detected, the system increases refresh frequency for adjacent vulnerable rows while maintaining normal operation elsewhere, optimizing the balance between reliability and energy consumption.
3Speed
If higher power supply voltage is used for write operations, then write speed is improved, but internal write time interval increases
Solution Approach 1:
The patent employs periodic pulse signals with optimized width and timing to control write operations. By using precisely timed periodic pulses rather than continuous high voltage, the system achieves fast write speeds while minimizing the duration of high-voltage states, thereby reducing the overall internal write time interval.
Solution Approach 2:
The system dynamically adjusts write operation parameters including voltage level and pulse width based on operational context. Higher voltages are applied only when needed for fast writes, while normal operations use lower voltages with shorter time intervals, optimizing the trade-off between write speed and time consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces internal write time intervals, minimizes performance degradation, and optimizes power consumption by managing row hammers effectively, thus enhancing the efficiency and reliability of semiconductor memory devices.
Implementation Method 1
a voltage level of the second power supply voltage is greater than a voltage level of the first power supply voltage
Data Source
AI summary
A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.