Semiconductor Row Main Signal Generation Timing Control
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Solution Overview
Problem
The existing semiconductor integrated circuits face challenges in tuning the activation timing of the row main signal, which affects the specifications of RAS to CAS delay time (tRCD) and precharge to RAS time (tRP), requiring costly mask revisions and increasing production time.
Innovation Solution
A semiconductor integrated circuit that utilizes test mode signals to control the delay time of the row main signal, allowing for flexible adjustment of activation timing without changing metal options in conductive lines, using a row main signal generation section with delay units and selection units to combine signals and provide a driving reference for row-series circuit units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the activation timing of the row main signal is tuned by opening or closing switches made of metal material to meet tRCD and tRP specifications, then the timing specifications are satisfied, but mask revisions are required which increase production time and costs
Solution Approach 1:
The patent changes the state of delay elements by controlling signal paths through transmission gates rather than permanently altering metal connections. The delay time is adjusted dynamically by enabling different delay element paths based on test mode signals, eliminating the need for mask revisions while meeting timing specifications.
Solution Approach 2:
The invention introduces dynamic control of delay time through transmission gates that can be switched on or off based on test mode signals. This dynamic adjustment mechanism allows timing optimization without permanent structural changes to the metal interconnect, resolving the contradiction between precision and ease of manufacture.
2Manufacturing precision
If mask revisions are performed to change metal options for delay time tuning, then timing specifications are met, but production time increases and costs increase
Solution Approach 1:
The patent implements parameter changes through software/control signals rather than hardware reconfiguration. Test mode signals control transmission gates to select different delay element paths, allowing precise delay time adjustment without mask revisions, thus maintaining high productivity while achieving manufacturing precision.
Solution Approach 2:
The invention replaces the mechanical process of mask revisions with an electrical/control-based system. Instead of physically changing metal connections through mask revisions, the patent uses transmission gates controlled by test mode signals to achieve the same delay time adjustment, eliminating the time-consuming mask revision process.
3Ease of manufacture
If test mode signals are used to control delay time through transmission gates, then production time and costs are reduced, but device complexity increases due to additional control logic
Solution Approach 1:
The transmission gates and delay elements serve multiple functions: they provide normal signal transmission paths during operation and enable delay time adjustment during testing. The same structural elements are used for both regular operation and timing tuning, reducing the need for separate dedicated components and limiting the increase in device complexity.
Solution Approach 2:
The system uses existing test mode signals already present in the DRAM architecture to control the delay time adjustment. Rather than requiring entirely new control signals or complex external control logic, the invention leverages existing self-service test signals to achieve delay tuning, minimizing the added complexity.
Data Source
AI summary
A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test mode signal.