Semiconductor Layer Fabrication via Sacrificial Etching
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Solution Overview
Problem
The miniaturization of semiconductor devices complicates the fabrication of layered structures in integrated circuits, particularly in achieving good electrical interconnection between layers, as existing methods like chemical mechanical polishing (CMP) can damage the device layer and require complex processes.
Innovation Solution
A method involving the formation of a laminate with a device layer, sacrificial layer, and protection layer, where the sacrificial layer is etched to expose the device layer, and CMP is used to remove parts of the dielectric and protection layers, allowing for the formation of through holes and conductive vias without direct contact with the polishing pad, thereby protecting the device layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to remove the electrically insulating layer, then the metal layer and semiconductor element can be exposed, but the device layer may be damaged
Solution Approach 1:
A sacrificial layer is introduced as an intermediary between the device layer and the polishing pad during CMP. This sacrificial layer absorbs the mechanical stress and contact from the polishing pad, preventing direct contact with and potential damage to the device layer while still allowing the CMP process to effectively remove the electrically insulating layer and expose the metal layer and semiconductor elements.
Solution Approach 2:
The sacrificial layer is formed on the device layer before the CMP process begins. This preliminary action prepares the structure to withstand the subsequent polishing operation, ensuring that the device layer is protected from direct mechanical contact with the polishing pad while the insulating layer removal is still achieved.
2Ease of manufacture
If the device layer is directly exposed by removing the electrically insulating layer, then electrical interconnection can be achieved, but the process complexity increases
Solution Approach 1:
The sacrificial layer is temporarily introduced to facilitate the CMP process and protect the device layer, then selectively removed in a subsequent step. This temporary structure serves its protective function during polishing and is then discarded, simplifying the overall process by enabling effective CMP without direct device layer contact while avoiding permanent structural complexity.
Solution Approach 2:
The fabrication process is segmented into distinct stages: forming the sacrificial layer, performing CMP to expose metal layers, and then selectively removing the sacrificial layer. This segmentation allows each step to be optimized independently, making the complex task of protecting the device layer during CMP manageable through separate, controlled operations.
3Reliability
If the device layer is protected during polishing, then damage risk is reduced, but additional process steps are required
Solution Approach 1:
The formation of the sacrificial layer is merged with the existing fabrication process flow, where the sacrificial layer is formed as part of the laminate structure before CMP. This integration means the protective function is achieved within the existing process framework rather than as a completely separate addition, minimizing the increase in overall process complexity while ensuring device layer protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures the device layer is protected during polishing, reduces process complexity, and enables self-aligned conductive metal layer formation, improving electrical interconnections and reducing the risk of damage to the device layer.
Implementation Method 1
removing part of the first dielectric layer and part of the protection layer by polishing
Implementation Method 2
etching the device layer, the sacrificial layer and the protection layer so as to obtain a patterned laminate
Implementation Method 3
etching the protection layer of the patterned laminate so as to expose the sacrificial layer
Implementation Method 4
etching the sacrificial layer of the patterned laminate so as to form an opening in the first dielectric layer
Data Source
AI summary
A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.