Semiconductor Planarization via Sacrificial Layer CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more highly integrated, the design rule reduction complicates the formation of interconnection lines and buried contacts, leading to level differences between cell and peripheral circuit regions, which can result in abnormal patterns and increased contact resistance.
Innovation Solution
A method involving the formation of bit line structures and gate structures with sacrificial layers, using a CMP process with a specific slurry composition to planarize the sacrificial layer, and forming multi-layered spacers to reduce level differences and improve contact areas, thereby simplifying the fabrication process and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are highly integrated with reduced design rules, then integration density increases, but level differences between cell region and peripheral circuit region increase causing abnormal patterns
Solution Approach 1:
A planarization layer is formed in advance to fill and flatten the grooves between bit line structures before subsequent processing. This preliminary planarization action prevents level differences from causing abnormal patterns in later fabrication steps, allowing high integration density to be achieved without sacrificing manufacturing precision.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary material that occupies the grooves between bit line structures during fabrication. This sacrificial layer serves as a placeholder that maintains structural integrity and enables controlled planarization, mediating between the need for high integration and the requirement for precise level control.
2Productivity
If design rules are reduced to increase integration density, then device size decreases, but formation of interconnection lines and buried contacts becomes more complicated
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming grooves between bit line structures, filling grooves with sacrificial layer, forming spacers, and selective removal. This segmentation breaks down the complex task of forming interconnection lines and buried contacts at reduced design rules into manageable steps, reducing overall process complexity while maintaining high integration density.
Solution Approach 2:
Grooves are formed preliminarily between bit line structures before forming interconnection lines and buried contacts. This preliminary groove formation simplifies subsequent steps by providing predefined pathways and separation zones, making the overall fabrication process less complex despite reduced design rules.
3Ease of manufacture
If level differences between cell region and peripheral circuit region are not controlled, then fabrication is simpler, but contact resistance increases and abnormal patterns form
Solution Approach 1:
A planarization layer is formed preliminarily to flatten level differences between cell and peripheral circuit regions before forming contacts. This preliminary planarization maintains low contact resistance and prevents abnormal patterns while keeping the fabrication process relatively simple through a single added step.
Solution Approach 2:
The surface topology parameter is changed from uneven to planar by forming the planarization layer. This parameter change in surface flatness simultaneously improves contact resistance and prevents abnormal patterns without significantly complicating the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces surface level differences between cell and peripheral circuit regions, prevents abnormal pattern formation, and enhances contact areas, improving the integration density and electrical characteristics of semiconductor devices.
Implementation Method 1
the sacrificial layer is planarized by a chemical mechanical polishing (CMP) process
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.