Semiconductor Device Manufacturing with Sacrificial Layer
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to complex manufacturing processes, resulting in reduced yield and significant variation in electrical characteristics, along with high parasitic capacitance and low on-state current, which hinders high integration, performance, and reliability.
Innovation Solution
A manufacturing method for semiconductor devices involving the formation of a sacrificial layer, insulators, and conductors using chemical mechanical polishing and wet etching techniques, with oxygen-containing insulators to supply oxygen to the oxide semiconductor, reducing oxygen vacancies and enhancing reliability and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional manufacturing processes are used for miniaturized transistors, then device integration is achieved, but manufacturing precision and electrical characteristic uniformity deteriorate
Solution Approach 1:
A sacrificial layer is formed in advance before the gate electrode, allowing precise definition of the channel region boundaries. This preliminary structure enables subsequent selective removal to create accurate channel openings, ensuring uniform electrical characteristics across miniaturized transistors while maintaining high integration density
Solution Approach 2:
The sacrificial layer acts as an intermediary structure that facilitates precise channel formation. It temporarily occupies the channel region space, allowing the gate electrode to be formed with exact dimensional control, and is subsequently removed to create the final channel opening with high precision
2Productivity
If transistor size is reduced for high integration, then device density increases, but parasitic capacitance increases and on-state current decreases
Solution Approach 1:
The gate electrode is extended in the vertical dimension to increase gate control effectiveness without increasing lateral footprint. This allows miniaturized transistors to maintain adequate on-state current while reducing parasitic capacitance through optimized gate-to-channel overlap in the vertical direction rather than lateral direction
3Productivity
If complex manufacturing processes are used for miniaturization, then device integration is achieved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The manufacturing process is segmented into distinct modular steps: forming the sacrificial layer, forming the gate electrode over it, and selectively removing the sacrificial layer. This segmentation transforms a complex miniaturization challenge into manageable sequential operations, reducing overall process difficulty while achieving high device integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables transistors with stable electrical characteristics, reduced parasitic capacitance, and increased on-state current, improving yield and productivity while allowing for easy adjustment of channel length, thus achieving high integration and performance.
Implementation Method 1
exposing a top surface of the sacrificial layer by a chemical mechanical polishing method
Implementation Method 2
removing the sacrificial layer by a wet etching method, thereby forming an opening in the first insulator
Implementation Method 3
oxygen-containing insulators to supply oxygen to the oxide semiconductor, reducing oxygen vacancies
Data Source
AI summary
A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a semiconductor device including the transistor are achieved. A semiconductor and a conductor are formed over a substrate, a sacrificial layer is formed over the conductor, and an insulator is formed to cover the sacrificial layer. After that, a top surface of the insulator is removed to expose a top surface of the sacrificial layer. The sacrificial layer and a region of the conductor overlapping with the sacrificial layer are removed, whereby a source region, a drain region, and an opening are formed. Next, a gate insulator and a gate electrode are formed in the opening.