Semiconductor Patterning via Sacrificial Mask and Spacer Etching
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Solution Overview
Problem
The miniaturization of semiconductor structures poses challenges in accurately forming two-dimensional (2D) and one-dimensional (1D) features without increasing process complexity and cost, as current photolithography techniques struggle to meet the demands of advanced semiconductor devices like DRAMs and flash memories.
Innovation Solution
A method involving the formation of a first patterned mask with sacrificial layers and spacers, followed by etching to create a second patterned mask, which is then used to precisely form 2D and 1D features in the target layer, allowing for accurate pattern transfer without additional complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography techniques are used to define structures, then the manufacturing process is simple and cost-effective, but the manufacturing precision deteriorates as feature sizes are reduced for miniaturization
Solution Approach 1:
The patterning process is divided into multiple sequential steps: forming a first patterned mask with first openings, filling with first sacrificial layer, forming patterned core layer with closed patterns and second openings, forming spacers, removing spacers to create third openings, etching first sacrificial layer and first patterned mask, removing first sacrificial layer to form second patterned mask, and finally etching target layer. This segmentation allows each step to contribute to the final precise pattern while using standard manufacturing techniques
Solution Approach 2:
The first patterned mask and first sacrificial layer are formed in advance before the final patterning step. The patterned core layer is formed on the first sacrificial layer with closed patterns that will define the final feature geometry. These preliminary structures serve as templates that guide subsequent etching processes to achieve the desired precise features
2Manufacturing precision
If photolithography techniques are used to define structures, then the process cost is low, but the manufacturing precision deteriorates with advancing miniaturization
Solution Approach 1:
The complex patterning task is broken down into manageable sequential steps using standard manufacturing equipment and materials. Each step (forming masks, filling sacrificial layers, forming core layers, creating spacers, selective removal) can be performed with existing process tools, avoiding the need for expensive new equipment while achieving higher precision
Solution Approach 2:
Sacrificial layers (first and second) are introduced as intermediary materials that temporarily occupy space during the patterning process. These sacrificial layers enable the formation of complex patterns by serving as placeholders that are selectively removed at different stages, allowing precise feature definition without requiring direct lithographic patterning of all features
3Manufacturing precision
If conventional photolithography is used, then the process is straightforward, but it cannot meet the demands of advanced semiconductor devices with finer features
Solution Approach 1:
The patterning process is divided into multiple sequential steps: forming a first patterned mask with first openings, filling with first sacrificial layer, forming patterned core layer with closed patterns and second openings, forming spacers, removing spacers to create third openings, etching first sacrificial layer and first patterned mask, removing first sacrificial layer to form second patterned mask, and finally etching target layer. This segmentation allows each step to contribute to the final precise pattern while using standard manufacturing techniques
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional structured patterning by forming vertical spacers on sidewalls of the patterned core layer. This dimensional transition enables the creation of complex 3D features with precise dimensional control, addressing the needs of advanced semiconductor devices that require finer and more complex structures
Data Source
AI summary
A method for preparing a semiconductor structure includes the following steps. A target layer is formed over a substrate. A first patterned mask is formed over the target layer and includes plural first openings separate from each other. The first openings are filled with a first sacrificial layer. A patterned core layer is formed on the first sacrificial layer and includes plural closed patterns and plural second openings within the closed patterns of the patterned core layer. Plural spacers are formed on sidewalls of the patterned core layer. The spacers are removed to form a plurality of third openings over the substrate. The first sacrificial layer and the first patterned mask are etched through the third openings. The first sacrificial layer is removed to form a second patterned mask on the target layer. The target layer is etched through the second patterned mask to form a patterned target layer.