Semiconductor Device Saturation Current Suppression Layer
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Solution Overview
Problem
Semiconductor devices face a trade-off between achieving low on-resistance and low saturation current, with existing technologies unable to simultaneously reduce both effectively, leading to potential device damage during load short-circuits.
Innovation Solution
A semiconductor device with a saturation current suppression layer comprising alternately arranged electric field block layers and JFET portions, along with a trench gate structure, where the JFET portions have varying impurity concentrations to control depletion layer extension and current path, allowing for low on-resistance and low saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the on-resistance is reduced to improve device performance, then the saturation current increases during load short-circuits, but this can cause device damage
Solution Approach 1:
The drift layer is divided into multiple regions with different impurity concentrations: a first drift layer region with lower impurity concentration and a second drift layer region with higher impurity concentration. This segmentation allows the device to achieve low on-resistance in the first region while limiting saturation current in the second region during short-circuit conditions.
Solution Approach 2:
Different regions of the drift layer are assigned different impurity concentrations to perform different functions. The first drift layer region has optimized low impurity concentration for low on-resistance operation, while the second drift layer region has higher impurity concentration to suppress saturation current during abnormal conditions, creating local quality variations that solve the contradiction.
2Reliability
If the impurity concentration in the drift layer is increased to reduce on-resistance, then the saturation current also increases, but if decreased to reduce saturation current, then on-resistance increases
Solution Approach 1:
The drift layer is segmented into two distinct regions with different impurity concentrations. The first region uses lower impurity concentration to suppress saturation current, while the second region uses higher impurity concentration to maintain low on-resistance, resolving the trade-off through spatial segmentation.
Solution Approach 2:
The solution moves from a single-dimensional impurity concentration profile to a two-dimensional structure with vertical layering. By stacking drift layer regions with different impurity concentrations in the vertical dimension, the patent achieves both low on-resistance and suppressed saturation current simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the semiconductor device to maintain low on-resistance while preventing high saturation current during load short-circuits, thereby improving the device's tolerance and reliability.
Implementation Method 1
by applying a gate voltage to the gate electrode and applying a voltage for a normal operation to the drain electrode as a drain voltage, a channel region is formed in a portion of the base region that contacts with the trench gate structure and a current flows between the source electrode and the drain electrode
Implementation Method 2
the JFET portions have varying impurity concentrations to control depletion layer extension and current path
Data Source
AI summary
A semiconductor device including a semiconductor element is provided. The semiconductor element includes a saturation current suppression layer formed above a drift layer and including electric field block layers arranged in a stripe manner and JFET portions arranged in a stripe manner. The electric field block layers and the JFET portions are alternately arranged. The semiconductor element includes trench gate structures. A longer direction of the trench gate structure intersects with a longer direction of the electric field block layer and a longer direction of JFET portion. The JFET portion includes a first layer having a first conductivity type impurity concentration larger than the drift layer and a second layer formed above the first layer and having a first conductivity type impurity concentration smaller than the first layer.