Semiconductor Sawing via Scribe Line Openings
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Solution Overview
Problem
The semiconductor industry faces challenges with signal delay in integrated circuits due to increased parasitic capacitance and resistance in interconnects, particularly when using low dielectric constant materials, which leads to issues like peeling, chipping, and delamination during the sawing process, reducing yield and causing defects.
Innovation Solution
A method involving photolithography and etching to remove portions of layers within scribe line areas, creating openings that allow for direct cutting of substrates without contacting high stress or weak low dielectric constant layers, thereby reducing the likelihood of crack, peeling, or delamination during the sawing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low dielectric constant materials are used in inter metal dielectric layers, then interconnect RC time constant is reduced, but peeling and delamination are more likely to occur during sawing
Solution Approach 1:
The patent applies preliminary action by forming protective structures (such as trench structures, reinforcement structures, or modified dielectric layers) in the scribe line areas before the sawing process. These structures are prepared in advance to prevent peeling and delamination that would occur during subsequent sawing operations, while maintaining the low dielectric constant material benefits in the functional areas.
Solution Approach 2:
The patent implements local quality by applying different structural modifications to specific locations. The scribe line areas receive special protective structures or modified dielectric layers, while the die areas maintain the original low dielectric constant interconnect structure. This localized approach prevents sawing-induced damage without compromising the overall low RC time constant performance.
2Ease of manufacture
If conventional sawing is performed on wafers with low dielectric constant materials, then manufacturing process is simple, but crack, peeling, or delamination occurs reducing yield
Solution Approach 1:
The patent forms protective structures or modifies dielectric layers in scribe line areas before sawing to prevent crack, peeling, or delamination. This preliminary preparation maintains relatively simple manufacturing by adding only one or two process steps before the existing sawing operation, while significantly improving yield by preventing defects.
Solution Approach 2:
The patent introduces intermediary structures (such as trench structures filled with different materials, or intermediate reinforcement layers) in the scribe line areas that act as mediators between the saw blade and the fragile low dielectric constant layers. These intermediary structures absorb or distribute the mechanical stress during sawing, preventing direct damage to the interconnect layers.
3Device complexity
If layers are not removed in scribe line areas, then manufacturing process is straightforward, but stress concentration causes peeling at die corners during sawing
Solution Approach 1:
The patent performs preliminary modification of the dielectric layers or formation of protective structures in the scribe line areas before sawing. This preliminary action reduces stress concentration at die corners by creating stress-distributing structures, thereby preventing peeling while adding minimal complexity to the manufacturing process.
Solution Approach 2:
The patent applies local quality by modifying only the scribe line areas where stress concentration occurs during sawing, while leaving the die areas unchanged. This localized modification reduces peeling risk at critical locations without requiring complex changes to the entire wafer structure or process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates defects such as peeling and delamination, improving the yield of semiconductor devices by reducing mechanical stress and allowing for precise cutting of substrates without affecting the interconnect layers, thus enhancing the reliability and performance of integrated circuits.
Implementation Method 1
A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings
Implementation Method 2
A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings
Data Source
AI summary
A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.