Semiconductor Scan Test Clock Synchronization via Buffer Mediator
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Solution Overview
Problem
Existing semiconductor devices face challenges in accelerating the clock speed during scan testing, as even with a lock-up latch, normal data transfer may not be possible, leading to issues like hold and setup violations.
Innovation Solution
The semiconductor device incorporates a counter circuit to generate a read signal when a predetermined count number is reached, a buffer to store and sequentially output test data, and a first scan test circuit to capture the test data, allowing for synchronization and acceleration of the clock speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lock-up latch is provided between scan shift registers to fix clock skew, then clock skew between different branches is corrected, but normal data transfer becomes impossible when clock is accelerated
Solution Approach 1:
A buffer is introduced as an intermediary component between the first and second scan shift registers. The buffer receives test data from the first scan shift register, stores it temporarily, and then outputs it to the second scan shift register. This intermediary structure allows the system to accommodate different clock frequencies between branches while maintaining reliable data transfer, resolving the contradiction between clock skew correction and data transfer capability.
2Productivity
If clock speed is accelerated to improve testing efficiency, then scan testing speed increases, but hold and setup violations occur preventing normal operation
Solution Approach 1:
The patent implements dynamic clock frequency control for different branches of the scan chain. The first scan shift register operates at a first clock frequency while the second scan shift register operates at a second clock frequency, allowing each branch to run at its optimal speed. This dynamic adjustment enables accelerated testing without causing hold or setup violations, as each branch's clock frequency is independently optimized.
Solution Approach 2:
The patent changes the clock frequency parameter differently for different branches of the scan chain. By setting distinct clock frequencies (first clock frequency for the first branch, second clock frequency for the second branch), the system can accelerate testing in each branch independently while maintaining proper timing relationships and avoiding hold/setup violations.
3Loss of time
If clock frequency is increased to reduce test time, then testing efficiency improves, but data transfer between scan chains becomes unreliable
Solution Approach 1:
The buffer serves as a mediator that decouples the timing requirements of different scan chain branches. It receives data from the first scan shift register at its own clock frequency and transfers it to the second scan shift register at its own clock frequency, ensuring reliable data transfer even when clock frequencies differ and test time is reduced.
Solution Approach 2:
By implementing dynamic clock frequency control where each scan chain branch operates at its own optimized frequency, the system can reduce overall test time while maintaining data transfer reliability. The buffer coordinates these different frequencies to ensure proper data synchronization across branches.
Data Source
AI summary
The technology provided enables the acceleration of the clock. The semiconductor device comprises a counter circuit configured to generate a read signal when the count number reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored when the read signal indicates a valid value, and a first scan test circuit that sequentially captures the test data output from the buffer.