Semiconductor Boundary Scan Clock Synchronization Control
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Solution Overview
Problem
Conventional semiconductor devices experience issues with controlling the output time of data through the scan data output channel during boundary scan tests, leading to unexpected toggling of the boundary test clock signal and premature output of data due to misalignment between the scan test entry signal and the boundary test clock signal phases.
Innovation Solution
A semiconductor device with a clock control unit that generates a synchronized boundary test clock signal in synchronization with the exit time of the boundary scan test mode, and latches that store and serially output data, with a control unit managing the output timing to prevent premature data release and ensure accurate data sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the scan test entry signal and boundary test clock signal operate independently without synchronization control, then the boundary scan test can be performed, but the output timing of data becomes unpredictable and may cause premature data output
Solution Approach 1:
The patent applies preliminary action by generating the boundary test clock signal in synchronization with the exit time of the boundary scan test mode before actual data output occurs. The clock control unit prepares the clock signal timing in advance to ensure that data output only happens at the correct moment, preventing premature output while maintaining reliable timing control.
2Reliability
If data is sequentially output through the boundary scan path, then connection state can be checked, but unexpected toggling of the boundary test clock signal may occur causing test errors
Solution Approach 1:
The patent implements feedback by using the exit time of the boundary scan test mode as a synchronization reference for generating the boundary test clock signal. The clock control unit continuously monitors the test mode state and adjusts the clock signal timing based on this feedback, ensuring that clock toggling only occurs at appropriate moments and preventing unexpected toggling that would cause test errors.
3Manufacturing precision
If the boundary test clock signal toggles independently of the scan test entry signal, then clock operation is simple, but data output timing becomes inaccurate
Solution Approach 1:
The clock control unit generates the boundary test clock signal in synchronization with the exit time of the boundary scan test mode, preparing the precise timing in advance. This preliminary synchronization ensures that clock toggling and data output occur at the exact correct moments, achieving high timing precision without requiring complex real-time adjustment mechanisms.
Data Source
AI summary
A semiconductor device includes a clock control unit configured to receive an external test clock signal in a boundary scan test mode and generate a boundary test clock signal in synchronization with an entry time point of the boundary scan test mode, and a plurality of latches configured to receive and store a plurality of data in parallel in a boundary capture test mode and form a boundary scan path to sequentially output the plurality of stored data in the boundary scan test mode in response to the boundary test clock signal.