Semiconductor Scan Circuit for Pin-Limited Fault Localization
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Solution Overview
Problem
Conventional semiconductor devices face challenges in detecting and specifying the point of setup violations due to limited pins, leading to bundled error signals and potential malfunctions in subsequent stages, with existing mechanisms failing to accurately identify the source of malfunctions.
Innovation Solution
A semiconductor device incorporating a plurality of logic circuits and judging circuits with a first register, delay means, comparator, and scanning means to compare data from logic circuits, allowing for the transmission of error signals and identification of malfunction points through a shift register mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple judging circuits are provided to detect setup violations at different points, then the ability to specify the point of malfunction is improved, but the number of pins required increases
Solution Approach 1:
Multiple error signals from different judging circuits are merged into a single error signal line using OR logic. The scanning circuit shares a common clock signal and control signals with the judging circuits, consolidating multiple pin requirements into fewer shared resources while maintaining the ability to identify malfunction locations through sequential scanning.
Solution Approach 2:
The patent introduces a time dimension through sequential scanning. Instead of simultaneously outputting error signals from multiple judging circuits requiring multiple pins, the system scans through judging circuits sequentially in time, using a single error signal line to present malfunction information at different time steps, thereby reducing the number of pins required.
2Device complexity
If error signals from multiple circuits are bundled using an OR tree, then the number of pins is reduced, but the ability to specify the point of malfunction is lost
Solution Approach 1:
The scanning circuit operates periodically, sequentially activating different judging circuits in a time-division manner. This periodic scanning allows the system to present error information from different circuits at different time periods through a single error signal line, enabling malfunction location identification without requiring multiple pins for simultaneous error output.
Solution Approach 2:
The scanning circuit performs preliminary sequential activation of judging circuits before final error detection. By pre-establishing the scanning sequence and using control signals to prepare the system state, the patent enables systematic identification of malfunction locations through time-sequential evaluation rather than simultaneous multi-pin output.
3Reliability
If the latch circuit opens in synchronization with the flip-flop circuit to detect setup violations, then timing constraint detection is enabled, but malfunctions may be induced in subsequent stages
Solution Approach 1:
The patent segments the detection function into separate judging circuits, each independently evaluating timing constraints at specific points in the data path. Each judging circuit operates as an isolated unit with its own flip-flop and latch, preventing the propagation of detection-related malfunctions to subsequent stages while maintaining comprehensive timing coverage through multiple segmented detection points.
Data Source
AI summary
An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.