Semiconductor Scan Test Output Control Circuit
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Solution Overview
Problem
In large-scale semiconductor devices, synchronizing clocks between hierarchical blocks for dynamic fault testing is challenging, leading to difficulties in detecting faults in combinational circuits between divisional circuits.
Innovation Solution
A semiconductor device architecture that includes a transmitting-side hierarchical block, a receiving-side hierarchical block, and an inter-block circuit, where the output control circuit generates a predetermined signal during scan tests, allowing fault detection without synchronizing clocks between the blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same clock as the scan FFs in the divisional circuit to be tested is applied to the peripheral scan FFs of the divisional circuit not to be tested to detect faults of combinational circuits between divisional circuits, then fault detection capability is improved, but clock synchronization difficulty increases when circuit scale is large
Solution Approach 1:
The semiconductor device is divided into multiple divisional circuits, each with its own scan FFs and combinational circuits. This segmentation allows independent testing of each divisional circuit while maintaining the ability to detect faults in combinational circuits between divisions through the peripheral scan FFs interface.
Solution Approach 2:
Peripheral scan FFs serve as intermediary elements between divisional circuits. These peripheral scan FFs can receive clocks from either their own divisional circuit or adjacent divisional circuits, acting as a mediator that enables fault detection in combinational circuits without requiring complex global clock synchronization.
2Ease of manufacture
If dynamic fault test is performed for each hierarchical block in a large-scale circuit, then test organization is simplified, but fault detection of combinational circuits between hierarchical blocks is lost
Solution Approach 1:
The peripheral scan FFs have multi-functionality: they serve as scan FFs for their own divisional circuit testing and simultaneously act as interfaces for detecting faults in combinational circuits between divisional circuits. This universal design allows simplified test organization while maintaining comprehensive fault detection coverage.
3Measurement precision
If scan test is performed with clock synchronization between transmitting-side and receiving-side hierarchical blocks, then test accuracy is improved, but test time increases due to synchronization overhead
Solution Approach 1:
Test patterns are pre-loaded into the scan chains of both transmitting-side and receiving-side hierarchical blocks before the actual test. This preliminary action allows the test to proceed without real-time clock synchronization during the test execution, reducing test time while maintaining test accuracy through the pre-established test conditions.
Data Source
AI summary
The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block. The test control circuit controls the output control circuit to output a predetermined signal as the output signal of the transmission-side hierarchical block regardless of the output signal of the first logic circuit when the scan test of the second logic circuit is performed.