Semiconductor Device Screen Layer and Amorphous Region Recrystallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As MOS transistor feature sizes decrease, it becomes challenging to reduce power consumption while maintaining reduced transistor size, leading to difficulties in suppressing the short channel effect and varying threshold voltage.
Innovation Solution
A method for fabricating a semiconductor device involves forming a screen layer doped with a first type impurity, an undoped semiconductor layer, a gate structure, and amorphous regions on both sides of the gate, followed by re-crystallization through heat treatment, which helps in suppressing the short channel effect and reducing threshold voltage variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If MOS transistor feature size is decreased, then power consumption is reduced and density is increased, but short channel effect becomes difficult to suppress and threshold voltage variation increases
Solution Approach 1:
The semiconductor structure is segmented into multiple distinct regions: a first doped region, a second doped region with different doping concentration, and an undoped region. This segmentation allows independent optimization of each region's properties to suppress short channel effect while maintaining low power consumption in scaled transistors
Solution Approach 2:
Different regions are assigned different doping concentrations tailored to their specific functions: the first doped region has one concentration level, the second doped region has a different concentration level, and the undoped region has zero doping. This local quality differentiation enables precise control of threshold voltage and suppression of short channel effects in miniaturized devices
2Productivity
If MOS transistor feature size is decreased, then density is increased, but short channel effect becomes difficult to suppress and threshold voltage variation increases
Solution Approach 1:
The semiconductor structure is segmented into multiple distinct regions: a first doped region, a second doped region with different doping concentration, and an undoped region. This segmentation allows independent optimization of each region's properties to suppress short channel effect while maintaining low power consumption in scaled transistors
Solution Approach 2:
Different regions are assigned different doping concentrations tailored to their specific functions: the first doped region has one concentration level, the second doped region has a different concentration level, and the undoped region has zero doping. This local quality differentiation enables precise control of threshold voltage and suppression of short channel effects in miniaturized devices
3Use of energy by moving object
If operating voltage is decreased to reduce power consumption, then power consumption is reduced, but short channel effect suppression becomes more difficult
Solution Approach 1:
Different regions are assigned different doping concentrations tailored to their specific functions: the first doped region has one concentration level, the second doped region has a different concentration level, and the undoped region has zero doping. This local quality differentiation enables precise control of threshold voltage and suppression of short channel effects in miniaturized devices
Solution Approach 2:
The doping structure is designed in advance with specific concentration gradients and region distributions before device operation. The multi-region doping configuration is established during fabrication to pre-compensate for short channel effects, enabling the device to maintain proper electrical characteristics even at lower operating voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses the short channel effect and decreases threshold voltage variation, improving the reliability and performance of semiconductor devices by minimizing Random Dopant Fluctuation and maintaining control over threshold voltage.
Implementation Method 1
forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity
Implementation Method 2
re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region
Implementation Method 3
re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region
Implementation Method 4
forming an amorphous region, which does not come in contact with the screen layer, in the semiconductor layer through performing a PAI (Pre Amorphous ion Implantation) process
Data Source
AI summary
A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.