Semiconductor Screen Layer Junction Leakage Reduction
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Solution Overview
Problem
Existing semiconductor transistor structures face challenges in achieving reduced junction leakage and controlled threshold voltage levels, particularly at nanometer scales, while avoiding expensive or unavailable tools and process control conditions.
Innovation Solution
The fabrication of semiconductor structures involves forming epitaxial screen layers with in-situ doping during growth, which helps in establishing a sharp dopant profile and reducing junction leakage, combined with selective epitaxial growth processes and shallow trench isolation to eliminate facets and achieve facetless physical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used at nanometer scales, then manufacturing cost is reduced, but junction leakage increases and threshold voltage control becomes difficult
Solution Approach 1:
The patent applies local quality by creating a screen layer with a specific dopant concentration profile (5×10^18 to 5×10^19 atoms per cm³) at a defined depth (5 nm to 10 nm) beneath the gate dielectric. This localized dopant structure selectively addresses junction leakage at the channel-to-drain junction interface without requiring expensive blanket process changes across the entire manufacturing workflow.
2Reliability
If dopant structures are optimized to reduce junction leakage, then transistor reliability improves, but manufacturing complexity increases
Solution Approach 1:
The screen layer is formed as a preliminary structure before final transistor fabrication steps. By pre-establishing the dopant profile at the appropriate depth and concentration, the patent simplifies subsequent processing while ensuring junction leakage is already mitigated before device assembly begins.
3Ease of operation
If screen layer depth and concentration are precisely controlled, then threshold voltage controllability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes specific parameter ranges for the screen layer: dopant concentration of 5×10^18 to 5×10^19 atoms per cm³ and depth of 5 nm to 10 nm beneath the gate dielectric interface. These parameter specifications provide a practical window that balances threshold voltage controllability with achievable manufacturing precision using conventional epitaxial growth and ion implantation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction of junction leakage, improved threshold voltage controllability, and consistent transistor performance, offering a cost-effective solution for reliable electronic manufacturing at nanometer scales.
Implementation Method 1
forming a screen layer by growing an epitaxial layer on the substrate and in-situ doping the screen layer during epitaxial growth
Data Source
AI summary
A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.