Semiconductor Chip Scribe Line Geometry for Stress Reduction
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Solution Overview
Problem
The fabrication of semiconductor devices often results in damage to the semiconductor material during the dicing process, and existing methods fail to adequately prevent or minimize this damage, which can lead to performance issues and defects in the devices.
Innovation Solution
The use of etching processes, such as plasma etching and wet etching, to separate semiconductor wafers into chips, creating scribe lines and side surfaces with specific geometries like polygonal lines and arc-shaped lines, which reduces mechanical stress and minimizes defects, and the incorporation of sacrificial structures for monitoring and alignment support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dicing process is used to separate semiconductor wafer into chips, then productivity is improved, but manufacturing precision deteriorates due to damage to semiconductor material
Solution Approach 1:
The patent replaces the mechanical dicing process with a plasma etching process to separate the semiconductor wafer into chips. This substitution eliminates mechanical contact and associated damage while maintaining efficient separation. The plasma etching uses reactive ions to selectively remove material along predefined scribe lines, achieving clean separations without the physical stress of blade-based dicing.
Solution Approach 2:
The patent changes the separation method from mechanical to chemical/plasma-based, fundamentally altering the process parameters. By using plasma etching with controlled gas chemistry and power parameters, the process achieves precise material removal without mechanical damage. The side surfaces are formed with specific geometries (polygonal lines with inner angles >90° or arc-shaped lines) through controlled plasma processing parameters.
2Ease of manufacture
If conventional dicing is used, then ease of manufacture is improved, but reliability deteriorates due to increased defects and mechanical stress
Solution Approach 1:
The patent replaces mechanical dicing with plasma etching, eliminating the mechanical contact that causes defects and stress. The plasma process uses reactive species to chemically etch the wafer along scribe lines, producing clean separations that preserve semiconductor material integrity and reduce defect formation.
Solution Approach 2:
The patent introduces arc-shaped side surfaces with specific curvatures to reduce stress concentration at sharp corners. The curved geometries distribute mechanical stress more evenly, preventing crack initiation and improving device reliability. The arc-shaped lines replace sharp 90° corners that would concentrate stress during subsequent handling and packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces defects and mechanical stress in semiconductor chips, enhancing their quality and performance by minimizing damage during fabrication and operation, and allows for more precise alignment and measurement of electronic properties.
Implementation Method 1
The use of etching processes, such as plasma etching and wet etching, to separate semiconductor wafers into chips
Implementation Method 2
The use of etching processes, such as plasma etching and wet etching, to separate semiconductor wafers into chips
Data Source
AI summary
A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.