Semiconductor Source/Drain Width Control via Selective Epitaxial Growth
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Solution Overview
Problem
Current semiconductor devices face challenges in optimizing the width of source/drain regions to minimize leakage currents and enhance integration density while maintaining excellent electrical characteristics.
Innovation Solution
The semiconductor device incorporates a selective epitaxial growth (SEG) layer for the source/drain regions, with a maximum width that is 1.3 times or less than the active region width, and includes a gate electrode intersecting and surrounding the channel layers, which helps control the shape and size of the source/drain regions to reduce leakage currents and improve electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source/drain region width is increased to improve electrical characteristics, then the electrical performance is improved, but the leakage current increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the width of source/drain regions to be 1.3 times or less the active region width, and by adjusting impurity concentrations in the SEG layer to optimize the balance between electrical characteristics and leakage current minimization
Solution Approach 2:
The patent implements local quality by creating different impurity concentration zones within the source/drain regions through selective epitaxial growth, with higher impurity concentrations near the channel interface to reduce resistance while maintaining lower overall concentrations to minimize leakage
2Object-generated harmful factors
If the source/drain region width is decreased to minimize leakage currents, then the leakage current is reduced, but the electrical characteristics deteriorate
Solution Approach 1:
The patent optimizes the width parameter to a specific range (1.3 times or less active region width) and adjusts impurity concentration parameters in the SEG layer to maintain excellent electrical characteristics while minimizing leakage currents
3Reliability
If the source/drain region width is increased to improve electrical characteristics, then the electrical performance is improved, but the integration density decreases
Solution Approach 1:
The patent optimizes the width parameter to 1.3 times or less the active region width, achieving a balance that maintains excellent electrical characteristics while maximizing integration density through compact device layout
4Area of stationary object
If the source/drain region width is decreased to enhance integration density, then the integration density is improved, but the electrical characteristics worsen
Solution Approach 1:
The patent precisely controls the source/drain region width parameter and impurity concentration parameters to achieve optimal integration density while maintaining excellent electrical characteristics through selective epitaxial growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes leakage currents and enhances integration density, resulting in improved electrical characteristics and reliability of the semiconductor device.
Implementation Method 1
a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer
Data Source
AI summary
A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.