Semiconductor Seal Ring Noise Isolation via Deep Well Layers
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Solution Overview
Problem
In semiconductor elements where analog and digital circuits are integrated, noise interference from digital circuits to analog circuits is a significant issue due to the close proximity of these circuits, leading to reliability concerns and signal degradation.
Innovation Solution
The implementation of a ring-shaped seal ring surrounding the circuits with electrical connections to external low-impedance nodes or capacity elements, and the use of deep n-type and n-type well layers to increase impedance and attenuate noise propagation, along with meandering seal ring designs and insulating layers to further reduce noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If analog and digital circuits are formed on one chip, then integration density is improved, but noise interference from digital circuit to analog circuit increases
Solution Approach 1:
The chip is divided into distinct analog and digital regions separated by a deep n-type well structure. This segmentation physically isolates the analog circuit from digital noise sources while maintaining overall integration on a single chip, thus resolving the contradiction between high integration density and noise interference.
Solution Approach 2:
A deep n-type well structure is introduced as an intermediary element between the analog and digital circuits. This intermediate structure acts as a noise barrier that blocks digital noise from propagating to the analog circuit, enabling both circuits to coexist on the same chip without significant interference.
2Object-affected harmful factors
If analog circuit is arranged far from digital circuit, then noise interference is reduced, but chip area increases
Solution Approach 1:
Instead of separating analog and digital circuits only in the planar dimension (increasing chip area), the invention introduces a vertical dimension by forming a deep n-type well structure that extends downward from the chip surface. This vertical separation allows close proximity arrangement while maintaining noise isolation, thus reducing chip area compared to planar separation methods.
3Object-affected harmful factors
If deep n-type well layer and n-type well layer are arranged to separate analog circuit, then noise propagation is attenuated, but device complexity increases
Solution Approach 1:
The deep n-type well structure combines multiple well layers (deep n-type well layer and n-type well layer) into a single integrated noise isolation mechanism. This merged structure achieves effective noise propagation attenuation while reducing the complexity that would result from implementing multiple separate isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise propagation from digital circuits to analog circuits, enhancing the reliability and signal integrity by increasing impedance and attenuating high-frequency signals, thereby minimizing the influence of digital circuit noise on analog circuits.
Implementation Method 1
a parasitic capacity C102 is formed at an interface between the deep n-type well layer 143 and the n-type well layer 144 on a side closer to the analog circuit 110, and a parasitic capacity C103 is formed at an interface between the deep n-type well layer 143 and the n-type well layer 144 on a side opposite to the side closer to the analog circuit 110
Implementation Method 2
the seal ring 130 is formed by alternately laminating vias 131 and wiring layers 132 on a high-concentration p-type semiconductor region 133 formed on the surface of the p-type semiconductor substrate 140
Data Source
AI summary
A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.