Semiconductor Seal Ring with Segmented Connection Layers
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Solution Overview
Problem
Existing seal ring structures in semiconductor fabrication have poor mechanical properties at the interface between metal and dielectric materials, leading to cracking and delamination during the chip sawing process, which compromises the protection of device regions and affects chip performance.
Innovation Solution
A semiconductor structure with a first seal ring structure that includes overlapping connection layers formed by discrete sub-connection layers, with conductive plugs extending into the dielectric layer between these layers, enhancing mechanical strength and preventing delamination or cracking from propagating to the device region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional multi-layer seal ring structure is formed during wiring layer fabrication, then the seal ring provides basic protection, but the interface between metal and dielectric materials has poor mechanical properties leading to cracking and delamination during chip sawing
Solution Approach 1:
The patent divides the continuous connection layer into multiple discrete sub-connection layers separated by dielectric material. This segmentation creates a stepped configuration where each sub-connection layer is mechanically isolated, preventing crack propagation through the entire seal ring structure during chip sawing while maintaining electrical connectivity through conductive plugs.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the seal ring. The sub-connection layers have reduced width compared to the overall seal ring, creating localized stress distribution. The dielectric material between sub-connection layers provides mechanical isolation, while conductive plugs provide localized electrical connection, optimizing both mechanical strength and electrical functionality in different regions.
2Reliability
If the seal ring structure uses stacked metal and insulating layers with via holes, then electrical connectivity is achieved, but the exposed sidewall surfaces of insulating films create moisture penetration paths
Solution Approach 1:
The patent transitions from a planar via-hole connection approach to a three-dimensional stepped structure with sub-connection layers extending laterally. This dimensional change allows the seal ring to cover and protect the sidewall surfaces of insulating films, blocking moisture penetration paths while maintaining electrical connectivity through the conductive plugs connecting the sub-connection layers.
Solution Approach 2:
The patent merges the electrical connection function (conductive plugs) with the moisture protection function (stepped seal ring structure). The sub-connection layers and conductive plugs work together as an integrated system that simultaneously provides electrical connectivity and physical barrier against moisture, eliminating the need for separate protective measures.
3Reliability
If connection layers are formed as continuous structures, then electrical connectivity is maximized, but mechanical stress during sawing causes delamination and cracking
Solution Approach 1:
The patent segments the continuous connection layer into multiple discrete sub-connection layers with dielectric material between them. This segmentation creates mechanical isolation that prevents stress concentration and crack propagation, while electrical connectivity is maintained through conductive plugs that connect the segmented layers, achieving both structural integrity and electrical functionality.
Solution Approach 2:
The patent incorporates dielectric material between the sub-connection layers as a cushioning element before the chip sawing process occurs. This dielectric layer absorbs and distributes mechanical stress, preventing delamination and cracking during sawing, while the conductive plugs ensure electrical connectivity is restored after stress relief.
Data Source
AI summary
Semiconductor structures are provided. A semiconductor structure includes a substrate having a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.