Semiconductor Seal Ring Stress Management

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional semiconductor devices experience chipping and cracking during the dicing process due to mechanical impact, with the passivation film peeling off, leading to reliability and moisture resistance issues.

Innovation Solution

A semiconductor device design featuring a seal ring surrounded by a first protective film with strategically formed openings and a cap layer, which blocks the transmission of impact and stress from the outside to the chip region, preventing peeling and corrosion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a seal ring is formed in the periphery of the chip region to prevent cracks from spreading, then the reliability of the semiconductor device is improved, but the passivation film peels off due to mechanical impact during dicing, causing harmful effects

Engineering Contradiction:

Improvecrack preventionVSAvoidpassivation film peeling

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The seal ring is segmented into alternating wiring portions and via portions, allowing the structure to absorb and distribute mechanical stress during dicing, preventing continuous crack propagation while maintaining protective function

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pad opening acts as an intermediary element that absorbs mechanical impact during dicing, preventing the force from transmitting to the passivation film and causing peeling, while the seal ring continues to provide crack protection

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the wafer is diced into individual chips, then productivity is improved, but chip regions near the scribe line are subjected to mechanical impact causing chipping and cracking

Engineering Contradiction:

Improvechip separationVSAvoidchip integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The seal ring is formed in advance in the periphery of the chip region before dicing, creating a protective barrier that prevents cracks from spreading during the subsequent dicing process, while the pad opening is strategically positioned to absorb impact forces

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The pad opening serves as a cushioning element positioned beforehand to absorb mechanical impact during dicing, protecting the chip region from chipping and cracking while allowing efficient chip separation

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS8841753B2Semiconductor device having seal wiring

Publication Date: 2014.09.23 NUVOTON TECH CORP JAPAN

AI summary

A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.