Semiconductor Seal Ring With Void Region For Crack Absorption

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Solution Overview

Problem

Conventional semiconductor devices face challenges in preventing cracks and moisture ingress during the dicing process, as the seal ring is prone to damage, leading to reduced reliability and increased capacitance between interconnects, which affects processing speed.

Innovation Solution

A semiconductor device with a seal ring surrounded by a void region, where voids are formed outside the seal ring to absorb and block cracks and stress, preventing them from reaching the seal ring and maintaining its protective function.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a seal ring is formed around a chip region to prevent crack propagation and moisture entry, then reliability is improved, but the seal ring is prone to damage during dicing process

Engineering Contradiction:
Improveprotection against moisture and crack propagationVSAvoidresistance to dicing impact
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

A void region is formed surrounding the seal ring before the dicing process. This void region acts as a cushion that absorbs mechanical impact and stress during dicing, preventing the seal ring from being damaged while maintaining its protective function against moisture and crack propagation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Strength

If the seal ring is made robust to withstand dicing impact, then strength is improved, but capacitance between interconnects increases affecting processing speed

Engineering Contradiction:
Improveresistance to dicing impactVSAvoidprocessing speed
Core Design Contradiction:
StrengthVSSpeed

Solution Approach 1:

The protective structure is segmented into two distinct functional regions: a void region for mechanical impact absorption and a seal ring for moisture and crack protection. This segmentation allows the void region to handle mechanical stress without requiring the seal ring to be overly robust, thereby minimizing capacitance between interconnects and maintaining processing speed.

Inventive Principle:
Principle #1Segmentation

3Strength

If voids are formed outside the seal ring to absorb impact, then protection against dicing damage is improved, but device complexity increases

Engineering Contradiction:
Improveprotection against dicing damageVSAvoidstructural complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The void region formation is merged with the existing seal ring formation process. Both structures are created during the same manufacturing sequence, integrating the protective void region into the standard device fabrication flow without requiring entirely separate processing steps, thus limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7795705B2Semiconductor device and manufacturing method thereof
Publication Date: 2010.09.14 PANNOVA SEMIC LLC
  • US7795705B2 patent drawing
  • US7795705B2 patent drawing
  • US7795705B2 patent drawing

AI summary

A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element.