Semiconductor Package Sealant Void Reduction via Cavity Ratio
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Solution Overview
Problem
Semiconductor packages often exhibit non-uniform sealant filling due to high resistance, resulting in large-sized voids within the sealant, as the flowing speed of the sealant slows down during encapsulation, leading to incomplete filling and non-uniform density.
Innovation Solution
Defining a predetermined ratio between the distance from the chip's back surface to the sealant and the distance from the chip's active surface to the substrate's upper surface, with a ratio of 2-5, to reduce flowing resistance and ensure uniform sealant filling, along with controlling the sealant's flow speed and vacuum pressure to minimize voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the cavity is filled with sealant using conventional methods, then the encapsulation process is completed, but the sealant flows non-uniformly due to high resistance, causing large-sized voids and non-uniform filling
Solution Approach 1:
The patent changes the geometric parameters of the cavity, specifically the ratio of the first distance (from chip back surface to cavity inner-top surface) to the second distance (from substrate upper surface to chip active surface), keeping it within 0.5-2. This parameter optimization reduces flowing resistance and ensures uniform sealant filling, eliminating the need for complex flow control mechanisms
Solution Approach 2:
The patent introduces a multi-dimensional approach by controlling the three-dimensional geometry of the cavity and the flow paths from multiple influxes. By optimizing the spatial arrangement and distance ratios in 3D space, the sealant flow is balanced across different dimensions, preventing stagnation and void formation
2Productivity
If the sealant flows quickly to fill the cavity uniformly, then filling efficiency is improved, but the flowing resistance increases causing non-uniform filling and voids
Solution Approach 1:
The patent optimizes the cavity geometry parameters, specifically the distance ratios, to reduce flowing resistance. This allows the sealant to flow quickly and uniformly simultaneously, achieving both high filling speed and uniform distribution without compromising either aspect
3Manufacturing precision
If the cavity geometry is optimized to reduce flowing resistance, then sealant fills uniformly, but the device structure becomes more complex
Solution Approach 1:
The patent achieves uniform sealant filling by optimizing geometric parameters (distance ratios within 0.5-2) rather than introducing complex structural features. This parameter-based approach maintains structural simplicity while achieving the desired filling uniformity, avoiding the need for additional components or complex cavity designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor package with reduced void size and uniform sealant distribution, preventing sealant stagnation and solidification issues, thus achieving a more compact and uniformly filled encapsulant.
Implementation Method 1
the flowing resistance of the sealant is reduced, the cavity is uniformly filled with the sealant
Data Source
AI summary
A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a plurality of conductive parts and a sealant. The conductive parts electrically connect an upper surface of the substrate and an active surface of the semiconductor chip. The sealant covers a back surface of the semiconductor chip, wherein the space between the upper surface of the substrate and the active surface of the semiconductor chip is filled with a portion of the sealant. The back surface of the semiconductor is spaced apart from a top surface of the sealant by a first distance, the upper surface of the substrate is spaced apart from the active surface of the semiconductor chip by a second distance, and the ratio of the first distance to the second distance is smaller than or equal to 5.