Semiconductor Sealing Void Structure for Dicing Crack Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively managing stress and moisture permeation during the dicing process, leading to potential cracks and structural integrity issues.
Innovation Solution
Incorporation of a first sealing portion with a void structure around the outer periphery of the core region to act as a crack stopper and moisture barrier, enhancing the structural integrity and preventing stress propagation during dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional solid sealing structure is used to prevent moisture permeation, then moisture barrier performance is improved, but stress accumulation and crack propagation during dicing worsen
Solution Approach 1:
The sealing portion is designed with a void (porous structure) instead of being completely solid. This void allows the sealing portion to absorb stress during dicing while still maintaining moisture barrier functionality through the surrounding insulating material, thus preventing crack propagation while managing moisture permeation.
Solution Approach 2:
The void in the sealing portion acts as a pre-designed stress absorption zone that cushions against dicing stresses before cracks can propagate into the core region. This beforehand cushioning prevents stress accumulation that would otherwise lead to structural failure during the dicing process.
2Strength
If the sealing portion is made completely solid to prevent cracks, then structural strength is improved, but stress management and crack stopper functionality worsen
Solution Approach 1:
The sealing portion incorporates a void creating a porous structure that prevents crack propagation while allowing stress to be absorbed and dissipated. The void acts as a crack stopper, preventing cracks from spreading into the core region while the surrounding insulating material provides the necessary moisture barrier.
Solution Approach 2:
The void in the sealing portion serves as an intermediary element that mediates between the conflicting requirements of crack resistance and stress management. It provides a controlled discontinuity that stops cracks while the overall sealing structure maintains structural integrity and moisture barrier functionality.
3Object-affected harmful factors
If the insulating layer extends completely over the substrate to maximize coverage, then moisture protection is improved, but stress concentration and dicing reliability worsen
Solution Approach 1:
The insulating layer is segmented by the void in the sealing portion, creating a controlled discontinuity. This segmentation allows the insulating layer to provide moisture protection while the void prevents stress concentration from propagating across the entire substrate, thus improving dicing reliability.
Solution Approach 2:
The void in the sealing portion provides beforehand cushioning by creating a stress absorption zone before stresses can propagate through the entire insulating layer. This prevents stress concentration that would otherwise compromise dicing reliability while maintaining moisture protection.
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate, a transistor, an insulating layer, and a first sealing portion. The substrate includes a first region, and a second region provided to surround an outer periphery of the first region. The transistor is provided on the substrate in the first region. The insulating layer is provided above the transistor and over the first region and the second region. The first sealing portion is provided to divide the insulating layer and surround the outer periphery of the first region in the second region. The first sealing portion includes a first void.