Semiconductor Security Circuit in Back-End Wiring Layers
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Solution Overview
Problem
Existing semiconductor devices face challenges in incorporating a security function without leaking design information, as the circuit with security features is easily identifiable and analyzable in the front end of line (FEOL), and there is a lack of secure functionality in the back end of line (BEOL).
Innovation Solution
A semiconductor device is designed with a security function circuit integrated in the back end of line (BEOL), utilizing a general-purpose semiconductor manufacturing process, with features such as polycrystalline semiconductor materials and physically unclonable functions (PUFs) like arbiter, ring oscillator, SRAM, and butterfly PUFs, which are less specifiable and analyzable, and can be formed in layers with a wiring pitch of 100 nm or more, without requiring miniaturization processes or expensive immersion ArF exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a circuit having a security function is formed in the front end of line (FEOL), then the security function can be implemented, but design information leaks to external contract semiconductor manufacturers and third parties
Solution Approach 1:
The patent moves the security function circuit from the traditional FEOL (front end of line) to the BEOL (back end of line), specifically to upper wiring layers (M5 or higher) with larger wiring pitch. This dimensional relocation in the vertical stacking direction allows the security circuit to be formed using general-purpose manufacturing processes rather than specialized miniaturization processes, thereby preventing design information leakage while maintaining security functionality.
2Reliability
If a circuit having a security function is formed in the front end of line (FEOL), then the security function can be implemented, but the position and content of the circuit are easily identified and analyzed
Solution Approach 1:
By relocating the security circuit to upper BEOL layers (M5 or higher) with larger wiring pitch, the circuit becomes less easily identifiable and analyzable. The increased wiring pitch and different layer position make it harder for imitators to locate and analyze the security circuit, while the circuit continues to perform its security function effectively.
3Loss of information
If a circuit having a security function is formed in the back end of line (BEOL) with wiring pitch of 100 nm or more, then design information is protected from leakage, but the miniaturization process required in FEOL is not needed
Solution Approach 1:
The patent applies different manufacturing precision requirements to different regions of the semiconductor device. The FEOL maintains tight wiring pitch and uses specialized miniaturization processes, while the BEOL security circuit layer (M5 or higher) uses larger wiring pitch (100 nm or more) and general-purpose manufacturing processes. This local differentiation allows each region to be optimized for its specific function while using appropriate manufacturing capabilities.
Data Source
AI summary
A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.