Semiconductor Device Security Logic for Fault Analysis
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Solution Overview
Problem
Microcontrollers with nonvolatile memories equipped with security technology allow only chip erase operations once security is set ON, preventing fault analysis by manufacturers, while those without security face risks of illegal access.
Innovation Solution
A semiconductor device with a nonvolatile memory and an interface that includes a security logic unit controlling security levels using preset security codes and a lock code, allowing mode switching between normal and test modes for fault analysis without compromising security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If security technology is applied to nonvolatile memory, then protection against illegal access is improved, but fault analysis capability deteriorates
Solution Approach 1:
The patent implements a dynamic security mechanism where the security level can be changed from a locked state (preventing all operations) to an unlocked state (allowing fault analysis operations). This is achieved through a security management unit that receives unlock signals and modifies the security level accordingly, enabling the system to adapt between protection mode and analysis mode.
Solution Approach 2:
The patent applies preliminary action by setting a specific security level before fault analysis is needed. The security management unit is configured to allow fault analysis operations only when the security level is in a predetermined state (unlocked), while maintaining protection in other states. This preliminary configuration enables both security and analysis capabilities without requiring permanent compromise of either.
2Difficulty of detecting and measuring
If chip erase operation is allowed, then fault analysis is improved, but security protection deteriorates
Solution Approach 1:
The patent enables dynamic control of operation permissions based on security level. When the security level is locked, only chip erase operations are permitted (maintaining some security). When the security level is unlocked, full fault analysis operations are enabled. This dynamic adjustment allows the system to balance security and analysis needs without permanently sacrificing either.
Solution Approach 2:
The patent applies local quality by differentiating the permission levels for different operations based on the security state. In the locked state, chip erase is permitted but read/write operations are restricted. In the unlocked state, all operations including read/write are permitted. This localized differentiation of permissions allows selective access control.
3Difficulty of detecting and measuring
If multiple operations are allowed on nonvolatile memory, then fault analysis is improved, but security against illegal access deteriorates
Solution Approach 1:
The patent implements a dynamic security mechanism where the security level can be changed from a locked state (preventing all operations) to an unlocked state (allowing fault analysis operations). This is achieved through a security management unit that receives unlock signals and modifies the security level accordingly, enabling the system to adapt between protection mode and analysis mode.
Solution Approach 2:
The patent applies preliminary action by setting a specific security level before fault analysis is needed. The security management unit is configured to allow fault analysis operations only when the security level is in a predetermined state (unlocked), while maintaining protection in other states. This preliminary configuration enables both security and analysis capabilities without requiring permanent compromise of either.
Data Source
AI summary
A semiconductor device includes a nonvolatile memory, and an interface configured to transfer data to and from the nonvolatile memory. The interface includes a security logic unit which controls a security level for the data written to the nonvolatile memory, in accordance with a plurality of preset security codes and a lock code that is written to a specific area in the nonvolatile memory.